\n

OPA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OPA_CTL (CTL)

OPA_STATUS (STATUS)

OPA_CALCTL (CALCTL)

OPA_CALST (CALST)


OPA_CTL (CTL)

OP Amplifier Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_CTL OPA_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPEN0 OPDOEN0 OPDOIEN0

OPEN0 : OP Amplifier 0 Enable Bit\nNote: OP Amplifier 0 output needs wait stable 20 s after OPEN0 is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier0 Disabled

#1 : 1

OP amplifier0 Enabled

End of enumeration elements list.

OPDOEN0 : OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disable OP amplifier0 schmitt trigger non-invert buffer

#1 : 1

Enable OP amplifier0 schmitt trigger non-invert buffer

End of enumeration elements list.

OPDOIEN0 : OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP Amplifier 0 digital output interrupt function Disabled

#1 : 1

OP Amplifier 0 digital output interrupt function Enabled

End of enumeration elements list.


OPA_STATUS (STATUS)

OP Amplifier Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_STATUS OPA_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPDO0 OPDOIF0

OPDO0 : OP Amplifier 0 Digital Output
bits : 0 - 0 (1 bit)
access : read-write

OPDOIF0 : OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write


OPA_CALCTL (CALCTL)

OP Amplifier Calibration Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_CALCTL OPA_CALCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALTRG0 CALRVS0

CALTRG0 : OP Amplifier 0 Calibration Trigger Bit\nNote: Before this bit is enabled, OPEN0 should be set in advance.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier 0 calibration is stopped; hardware auto clear

#1 : 1

OP amplifier 0 calibration is started

End of enumeration elements list.

CALRVS0 : OPA0 Calibration Reference Voltage Selection
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREF is

#1 : 1

VREF from high vcm to low vcm

End of enumeration elements list.


OPA_CALST (CALST)

OP Amplifier Calibration Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA_CALST OPA_CALST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE0 CALNS0 CALPS0

DONE0 : OP Amplifier 0 Calibration Done Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Calibrating

#1 : 1

Calibration Done

End of enumeration elements list.

CALNS0 : OP Amplifier 0 Calibration Result Status for NMOS
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.

CALPS0 : OP Amplifier 0 Calibration Result Status for PMOS
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.



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