PDMA_CHCTL (CHCTL)

PDMA_STOP (STOP)

PDMA_SWREQ (SWREQ)

PDMA_TRGSTS (TRGSTS)

PDMA_PRISET (PRISET)

PDMA_PRICLR (PRICLR)

PDMA_INTEN (INTEN)

PDMA_INTSTS (INTSTS)

PDMA_ABTSTS (ABTSTS)

PDMA_TDSTS (TDSTS)

PDMA_SCATSTS (SCATSTS)

PDMA_TACTSTS (TACTSTS)

PDMA_TOUTEN (TOUTEN)

PDMA_TOUTIEN (TOUTIEN)

PDMA_SCATBA (SCATBA)

PDMA_TOC0_1 (TOC0_1)

PDMA_TOC2_3 (TOC2_3)

PDMA_TOC4_5 (TOC4_5)

PDMA_TOC6_7 (TOC6_7)

PDMA_REQSEL0_3 (REQSEL0_3)

PDMA_REQSEL4_7 (REQSEL4_7)

PDMA_REQSEL8_11 (REQSEL8_11)

CHENn : PDMA Channel Enable Bit\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote1: If software stops corresponding PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.\nNote3: CHEN8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STOPn : PDMA Transfer Stop Control Register (Write Only)\nUser can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).\nBy bit field:\nBy write 0xFFFF_FFFF to PDMA_STOP:\nSetting all PDMA_STOP bit to '1' will generate software reset to reset internal state machine (the DSCT will not be reset). When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'. \nNote1: User can read channel enable bit to know if the on-going transfer is finished.\nNote2: STOP8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQn : PDMA Software Request Register (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote2: If user does not enable corresponding PDMA channel, the software request will be ignored.\nNote3: SWREQ8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQSTSn : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote1: If software stops corresponding PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.\nNote2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.\nNote3: REQSTS8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FPRISETn : PDMA Fixed Priority Setting Register\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote1: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.\nNote2: FPRISET8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRICLRn : PDMA Fixed Priority Clear Register (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote1: User can read PDMA_PRISET register to know the channel priority.\nNote2: FPRICLR8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : write-only

Enumeration:

End of enumeration elements list.

INTENn : PDMA Interrupt Enable Register\nThis field is used for enabling PDMA channel[n] interrupt.\nNote: INTEN8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read-only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF : Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TEIF : Table Empty Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode. User can read TEIF register to indicate which channel finished transfer.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQTOFn : Request Time-out Flag for Each Channel [N] (M45xD/M45xC Only)\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
bits : 8 - 15 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIFn : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: ABTIF8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIFn : Transfer Done Flag Register\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.\nNote: TDIF8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TEMPTYFn : Scatter-gather Table Empty Flag Register\nThis bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn (PDMA_SWREQ[11:0]) set to high or channel has finished transmission and the operation mode is Stop mode. User can write 1 to clear these bits.\nNote: TEMPTYF8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXACTFn : Transfer on Active Flag Register (Read Only)\nThis bit indicates which PDMA channel is in active.\nNote: TXACTF8~11 is M45xG/M45xE only.
bits : 0 - 11 (12 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUTENn : PDMA Time-out Enable Bits
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTIENn : PDMA Time-out Interrupt Enable Bits
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCATBA : PDMA Scatter-gather Descriptor Table Address Register\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write

TOC0 : Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write

TOC1 : Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write

TOC2 : Time-out Period Counter for Channel 2\nThis controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write

TOC3 : Time-out Period Counter for Channel 3\nThis controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write

TOC4 : Time-out Period Counter for Channel 4\nThis controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write

TOC5 : Time-out Period Counter for Channel 5\nThis controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write

TOC6 : Time-out Period Counter for Channel 6\nThis controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.
bits : 0 - 15 (16 bit)
access : read-write

TOC7 : Time-out Period Counter for Channel 7\nThis controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
bits : 16 - 31 (16 bit)
access : read-write

REQSRC0 : Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral can't assign to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write

REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 4 (5 bit)
access : read-write

REQSRC5 : Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC6 : Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC7 : Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write

REQSRC8 : Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 4 (5 bit)
access : read-write

REQSRC9 : Channel 9 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 12 (5 bit)
access : read-write

REQSRC10 : Channel 10 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 20 (5 bit)
access : read-write

REQSRC11 : Channel 11 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 11. User can configure the peripheral setting by REQSRC11. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 28 (5 bit)
access : read-write