\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RTC_INIT (INIT)

RTC_CAL (CAL)

RTC_LXTCTL (LXTCTL)

RTC_LXTOCTL (LXTOCTL)

RTC_LXTICTL (LXTICTL)

RTC_TAMPCTL (TAMPCTL)

RTC_CLKFMT (CLKFMT)

RTC_WEEKDAY (WEEKDAY)

RTC_TALM (TALM)

RTC_CALM (CALM)

RTC_LEAPYEAR (LEAPYEAR)

RTC_INTEN (INTEN)

RTC_INTSTS (INTSTS)

RTC_TICK (TICK)

RTC_TAMSK (TAMSK)

RTC_CAMSK (CAMSK)

RTC_SPRCTL (SPRCTL)

RTC_RWEN (RWEN)

RTC_SPR0 (SPR0)

RTC_SPR1 (SPR1)

RTC_SPR2 (SPR2)

RTC_SPR3 (SPR3)

RTC_SPR4 (SPR4)

RTC_SPR5 (SPR5)

RTC_SPR6 (SPR6)

RTC_SPR7 (SPR7)

RTC_SPR8 (SPR8)

RTC_SPR9 (SPR9)

RTC_SPR10 (SPR10)

RTC_SPR11 (SPR11)

RTC_SPR12 (SPR12)

RTC_SPR13 (SPR13)

RTC_SPR14 (SPR14)

RTC_SPR15 (SPR15)

RTC_FREQADJ (FREQADJ)

RTC_SPR16 (SPR16)

RTC_SPR17 (SPR17)

RTC_SPR18 (SPR18)

RTC_SPR19 (SPR19)

RTC_TIME (TIME)


RTC_INIT (INIT)

RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INIT RTC_INIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIT_ACTIVE INIT

INIT_ACTIVE : RTC Active Status (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC is at reset state

#1 : 1

RTC is at normal active state

End of enumeration elements list.

INIT : RTC Initiation\nWhen RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state. Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.\nThe INIT is a write-only field and read value will be always 0.
bits : 1 - 31 (31 bit)
access : read-write


RTC_CAL (CAL)

RTC Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CAL RTC_CAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY TENDAY MON TENMON YEAR TENYEAR

DAY : 1-Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write


RTC_LXTCTL (LXTCTL)

RTC 32.768 KHz Oscillator Control Register
address_offset : 0x100 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_LXTCTL RTC_LXTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LXTEN GAIN

LXTEN : Backup Domain 32K Oscillator Enable Bit\nThis bit controls 32 kHz oscillator on/off. User can set either LXTEN in RTC battery power domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator. If this bit is set 1, X32 kHz oscillator keep running after system core power is turned off, if this bit is clear to 0, oscillator is turned off when system core power is turned off.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Oscillator is Disabled

#1 : 1

Oscillator is Enabled

End of enumeration elements list.

GAIN : Oscillator Gain Option\nUser can select oscillator gain according to crystal external loading and operating temperature range. The larger gain value corresponding to stronger driving capability and higher power consumption.
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 0

L0 mode

#001 : 1

L1 mode

#010 : 2

L2 mode

#011 : 3

L3 mode

#100 : 4

L4 mode

#101 : 5

L5 mode

#110 : 6

L6 mode

#111 : 7

L7 mode (Default)

End of enumeration elements list.


RTC_LXTOCTL (LXTOCTL)

X32KO Pin Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_LXTOCTL RTC_LXTOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPMODE DOUT CTLSEL

OPMODE : GPF0 Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

X32KO (PF.0) is input only mode, without pull-up resistor

#01 : 1

X32KO (PF.0) is output push pull mode

#10 : 2

X32KO (PF.0) is open drain mode

#11 : 3

X32KO (PF.0) is input only mode with internal pull up

End of enumeration elements list.

DOUT : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

X32KO (PF.0) output low

#1 : 1

X32KO (PF.0) output high

End of enumeration elements list.

CTLSEL : IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

X32KO (PF.0) pin I/O function is controlled by GPIO module. It becomes floating when system power is turned off

#1 : 1

X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off

End of enumeration elements list.


RTC_LXTICTL (LXTICTL)

X32KI Pin Control Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_LXTICTL RTC_LXTICTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPMODE DOUT CTLSEL

OPMODE : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

X32KI (PF.1) is input only mode, without pull-up resistor

#01 : 1

X32KI (PF.1) is output push pull mode

#10 : 2

X32KI (PF.1) is open drain mode

#11 : 3

X32KI (PF.1) is input only mode with internal pull up

End of enumeration elements list.

DOUT : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

X32KI (PF.1) output low

#1 : 1

X32KI (PF.1) output high

End of enumeration elements list.

CTLSEL : IO Pin State Backup Selection\nWhen low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function. User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

X32KI (PF.1) pin I/O function is controlled by GPIO module. It becomes floating state when system power is turned off

#1 : 1

X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin keeps the previous state after system power is turned off

End of enumeration elements list.


RTC_TAMPCTL (TAMPCTL)

TAMPER Pin Control Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TAMPCTL RTC_TAMPCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPMODE DOUT CTLSEL

OPMODE : IO Operation Mode
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#00 : 0

TAMPER (PF.2) is input only mode, without pull-up resistor

#01 : 1

TAMPER (PF.2) is output push pull mode

#10 : 2

TAMPER (PF.2) is open drain mode

#11 : 3

TAMPER (PF.2) is input only mode with internal pull up

End of enumeration elements list.

DOUT : IO Output Data
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

TAMPER (PF.2) output low

#1 : 1

TAMPER (PF.2) output high

End of enumeration elements list.

CTLSEL : IO Pin State Backup Selection\nWhen tamper function is disabled, TAMPER pin can be used as GPIO function. User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

TAMPER (PF.2) I/O function is controlled by GPIO module. It becomes floating state when system power is turned off

#1 : 1

TAMPER (PF.2) I/O function is controlled by VBAT power domain. PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1. I/O pin state keeps previous state after system power is turned off

End of enumeration elements list.


RTC_CLKFMT (CLKFMT)

RTC Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CLKFMT RTC_CLKFMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _24HEN

_24HEN : 24-hour / 12-hour Time Scale Selection\nIndicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

12-hour time scale with AM and PM indication selected

#1 : 1

24-hour time scale selected

End of enumeration elements list.


RTC_WEEKDAY (WEEKDAY)

RTC Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_WEEKDAY RTC_WEEKDAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WEEKDAY

WEEKDAY : Day of the Week Register
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Sunday

#001 : 1

Monday

#010 : 2

Tuesday

#011 : 3

Wednesday

#100 : 4

Thursday

#101 : 5

Friday

#110 : 6

Saturday

#111 : 7

Reserved.

End of enumeration elements list.


RTC_TALM (TALM)

RTC Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TALM RTC_TALM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC TENSEC MIN TENMIN HR TENHR

SEC : 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENSEC : 10-Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

MIN : 1-Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMIN : 10-Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

HR : 1-Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENHR : 10-hour Time Digit of Alarm Setting (0~2)\nWhen RTC runs as 12-hour time scale mode, the high bit of TENHR (RTC_TIME[21]) means AM/PM indication.
bits : 20 - 21 (2 bit)
access : read-write


RTC_CALM (CALM)

RTC Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CALM RTC_CALM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAY TENDAY MON TENMON YEAR TENYEAR

DAY : 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENDAY : 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

MON : 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMON : 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

YEAR : 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENYEAR : 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write


RTC_LEAPYEAR (LEAPYEAR)

RTC Leap Year Indicator Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_LEAPYEAR RTC_LEAPYEAR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEAPYEAR

LEAPYEAR : Leap Year Indication Register (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

This year is not a leap year

#1 : 1

This year is leap year

End of enumeration elements list.


RTC_INTEN (INTEN)

RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INTEN RTC_INTEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALMIEN TICKIEN SNPDIEN

ALMIEN : Alarm Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Alarm interrupt Disabled

#1 : 1

RTC Alarm interrupt Enabled

End of enumeration elements list.

TICKIEN : Time Tick Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Time Tick interrupt Disabled

#1 : 1

RTC Time Tick interrupt Enabled

End of enumeration elements list.

SNPDIEN : Snoop Detection Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Snoop detected interrupt Disabled

#1 : 1

Snoop detected interrupt Enabled

End of enumeration elements list.


RTC_INTSTS (INTSTS)

RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INTSTS RTC_INTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALMIF TICKIF SNPDIF

ALMIF : RTC Alarm Interrupt Flag\nWhen RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1. Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.\nNote: Write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Alarm condition is not matched

#1 : 1

Alarm condition is matched

End of enumeration elements list.

TICKIF : RTC Time Tick Interrupt Flag\nWhen RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1. Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.\nNote: Write 1 to clear to clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Tick condition does not occur

#1 : 1

Tick condition occur

End of enumeration elements list.

SNPDIF : Snoop Detect Interrupt Flag\nWhen tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1. Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.\nNote: Write 1 to clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

No snoop event is detected

#1 : 1

Snoop event is detected

End of enumeration elements list.


RTC_TICK (TICK)

RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TICK RTC_TICK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TICK

TICK : Time Tick Register\nThese bits are used to select RTC time tick period for Periodic Time Tick Interrupt request. \nNote: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

Time tick is 1 second

#001 : 1

Time tick is 1/2 second

#010 : 2

Time tick is 1/4 second

#011 : 3

Time tick is 1/8 second

#100 : 4

Time tick is 1/16 second

#101 : 5

Time tick is 1/32 second

#110 : 6

Time tick is 1/64 second

#111 : 7

Time tick is 1/28 second

End of enumeration elements list.


RTC_TAMSK (TAMSK)

RTC Time Alarm Mask Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TAMSK RTC_TAMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSEC MTENSEC MMIN MTENMIN MHR MTENHR

MSEC : Mask 1-Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENSEC : Mask 10-Sec Time Digit of Alarm Setting (0~5)
bits : 1 - 1 (1 bit)
access : read-write

MMIN : Mask 1-Min Time Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMIN : Mask 10-Min Time Digit of Alarm Setting (0~5)
bits : 3 - 3 (1 bit)
access : read-write

MHR : Mask 1-Hour Time Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENHR : Mask 10-Hour Time Digit of Alarm Setting (0~2)
bits : 5 - 5 (1 bit)
access : read-write


RTC_CAMSK (CAMSK)

RTC Calendar Alarm Mask Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CAMSK RTC_CAMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MDAY MTENDAY MMON MTENMON MYEAR MTENYEAR

MDAY : Mask 1-Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 0 (1 bit)
access : read-write

MTENDAY : Mask 10-Day Calendar Digit of Alarm Setting (0~3)
bits : 1 - 1 (1 bit)
access : read-write

MMON : Mask 1-Month Calendar Digit of Alarm Setting (0~9)
bits : 2 - 2 (1 bit)
access : read-write

MTENMON : Mask 10-Month Calendar Digit of Alarm Setting (0~1)
bits : 3 - 3 (1 bit)
access : read-write

MYEAR : Mask 1-Year Calendar Digit of Alarm Setting (0~9)
bits : 4 - 4 (1 bit)
access : read-write

MTENYEAR : Mask 10-Year Calendar Digit of Alarm Setting (0~9)
bits : 5 - 5 (1 bit)
access : read-write


RTC_SPRCTL (SPRCTL)

RTC Spare Functional Control Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPRCTL RTC_SPRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNPDEN SNPTYPE0 SPRRWEN SNPTYPE1 SPRCSTS SPRRWRDY

SNPDEN : Snoop Detection Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

TAMPER pin detection is Disabled

#1 : 1

TAMPER pin detection is Enabled

End of enumeration elements list.

SNPTYPE0 : Snoop Detection Level\nThis bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Low level/Falling edge detection

#1 : 1

High level/Rising edge detection.

End of enumeration elements list.

SPRRWEN : Spare Register Enable Bit\nNote: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Spare register is Disabled

#1 : 1

Spare register is Enabled

End of enumeration elements list.

SNPTYPE1 : Snoop Detection Mode\nThis bit controls TAMPER pin is edge or level detection
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level detection

#1 : 1

Edge detection

End of enumeration elements list.

SPRCSTS : SPR Clear Flag \nThis bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.\nWrites 1 to clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

Spare register content is not cleared

#1 : 1

Spare register content is cleared

End of enumeration elements list.

SPRRWRDY : SPR Register Ready\nThis bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.\nAfter user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.\nNote: This bit is read only and any write to it won't take any effect.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress

#1 : 1

RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed

End of enumeration elements list.


RTC_RWEN (RWEN)

RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_RWEN RTC_RWEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RWEN RWENF

RWEN : RTC Register Access Enable Password (Write Only)\nWriting 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
bits : 0 - 15 (16 bit)
access : write-only

RWENF : RTC Register Access Enable Flag (Read Only)\nThis bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC register read/write Disabled

#1 : 1

RTC register read/write Enabled

End of enumeration elements list.


RTC_SPR0 (SPR0)

RTC Spare Register 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR0 RTC_SPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE

SPARE : Spare Register\nThis field is used to store back-up information defined by user.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.\nBefore storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.
bits : 0 - 31 (32 bit)
access : read-write


RTC_SPR1 (SPR1)

RTC Spare Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR1 RTC_SPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR2 (SPR2)

RTC Spare Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR2 RTC_SPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR3 (SPR3)

RTC Spare Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR3 RTC_SPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR4 (SPR4)

RTC Spare Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR4 RTC_SPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR5 (SPR5)

RTC Spare Register 5
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR5 RTC_SPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR6 (SPR6)

RTC Spare Register 6
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR6 RTC_SPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR7 (SPR7)

RTC Spare Register 7
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR7 RTC_SPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR8 (SPR8)

RTC Spare Register 8
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR8 RTC_SPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR9 (SPR9)

RTC Spare Register 9
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR9 RTC_SPR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR10 (SPR10)

RTC Spare Register 10
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR10 RTC_SPR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR11 (SPR11)

RTC Spare Register 11
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR11 RTC_SPR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR12 (SPR12)

RTC Spare Register 12
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR12 RTC_SPR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR13 (SPR13)

RTC Spare Register 13
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR13 RTC_SPR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR14 (SPR14)

RTC Spare Register 14
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR14 RTC_SPR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR15 (SPR15)

RTC Spare Register 15
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR15 RTC_SPR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_FREQADJ (FREQADJ)

RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_FREQADJ RTC_FREQADJ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACTION INTEGER

FRACTION : Fraction Part\nNote: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
bits : 0 - 5 (6 bit)
access : read-write

INTEGER : Integer Part
bits : 8 - 11 (4 bit)
access : read-write


RTC_SPR16 (SPR16)

RTC Spare Register 16
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR16 RTC_SPR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR17 (SPR17)

RTC Spare Register 17
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR17 RTC_SPR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR18 (SPR18)

RTC Spare Register 18
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR18 RTC_SPR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR19 (SPR19)

RTC Spare Register 19
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR19 RTC_SPR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_TIME (TIME)

RTC Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TIME RTC_TIME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC TENSEC MIN TENMIN HR TENHR

SEC : 1-Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

TENSEC : 10-Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write

MIN : 1-Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

TENMIN : 10-Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write

HR : 1-Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

TENHR : 10-hour Time Digit (0~2)\nWhen RTC runs as 12-hour time scale mode, RTC_TIME[21] (the high bit of TENHR[1:0]) means AM/PM indication. (If RTC_TIME[21] is 1, it indicates PM time message.)
bits : 20 - 21 (2 bit)
access : read-write



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