\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x33C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xE00 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
IRQ0 ~ IRQ63 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ63 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ63 Set-pending Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ63 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ63 Clear-pending Control Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ0 ~ IRQ63 Active Bit Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ0 ~ IRQ63 Active Bit Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ0 ~ IRQ63 Priority Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4n_0 : Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 4 - 7 (4 bit)
access : read-write
PRI_4n_1 : Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 12 - 15 (4 bit)
access : read-write
PRI_4n_2 : Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 20 - 23 (4 bit)
access : read-write
PRI_4n_3 : Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 28 - 31 (4 bit)
access : read-write
IRQ0 ~ IRQ63 Priority Control Register
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4n_0 : Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 4 - 7 (4 bit)
access : read-write
PRI_4n_1 : Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 12 - 15 (4 bit)
access : read-write
PRI_4n_2 : Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 20 - 23 (4 bit)
access : read-write
PRI_4n_3 : Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 28 - 31 (4 bit)
access : read-write
IRQ0 ~ IRQ63 Set-enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ63 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ0 ~ IRQ63 Clear-enable Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
Software Trigger Interrupt Registers
address_offset : 0xE00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTID : Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-63. For example, a value of 0x03 specifies interrupt IRQ3.
bits : 0 - 8 (9 bit)
access : read-write
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