\n

NVIC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x300 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x80 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x100 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x180 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x33C Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0xE00 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected

Registers

NVIC_ISER1 (ISER1)

NVIC_ISPR1 (ISPR1)

NVIC_ISPR2 (ISPR2)

NVIC_ICPR1 (ICPR1)

NVIC_ICPR2 (ICPR2)

NVIC_IABR1 (IABR1)

NVIC_IABR2 (IABR2)

NVIC_IPR1 (IPR1)

NVIC_IPR2 (IPR2)

NVIC_ISER2 (ISER2)

NVIC_ICER1 (ICER1)

NVIC_ICER2 (ICER2)

STIR


NVIC_ISER1 (ISER1)

IRQ0 ~ IRQ63 Set-enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER1 NVIC_ISER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ISPR1 (ISPR1)

IRQ0 ~ IRQ63 Set-pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR1 NVIC_ISPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt is not pending

1 : 1

Changes interrupt state to pending.\nInterrupt is pending

End of enumeration elements list.


NVIC_ISPR2 (ISPR2)

IRQ0 ~ IRQ63 Set-pending Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR2 NVIC_ISPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt is not pending

1 : 1

Changes interrupt state to pending.\nInterrupt is pending

End of enumeration elements list.


NVIC_ICPR1 (ICPR1)

IRQ0 ~ IRQ63 Clear-pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR1 NVIC_ICPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt is not pending

1 : 1

Removes pending state an interrupt.\nInterrupt is pending

End of enumeration elements list.


NVIC_ICPR2 (ICPR2)

IRQ0 ~ IRQ63 Clear-pending Control Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR2 NVIC_ICPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALPEND

CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR2 registers remove the pending state from interrupts, and show which interrupts are pending\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt is not pending

1 : 1

Removes pending state an interrupt.\nInterrupt is pending

End of enumeration elements list.


NVIC_IABR1 (IABR1)

IRQ0 ~ IRQ63 Active Bit Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR1 NVIC_IABR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

interrupt not active

1 : 1

interrupt active

End of enumeration elements list.


NVIC_IABR2 (IABR2)

IRQ0 ~ IRQ63 Active Bit Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR2 NVIC_IABR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

interrupt not active

1 : 1

interrupt active

End of enumeration elements list.


NVIC_IPR1 (IPR1)

IRQ0 ~ IRQ63 Priority Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR1 NVIC_IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4n_0 PRI_4n_1 PRI_4n_2 PRI_4n_3

PRI_4n_0 : Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 4 - 7 (4 bit)
access : read-write

PRI_4n_1 : Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 12 - 15 (4 bit)
access : read-write

PRI_4n_2 : Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 20 - 23 (4 bit)
access : read-write

PRI_4n_3 : Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 28 - 31 (4 bit)
access : read-write


NVIC_IPR2 (IPR2)

IRQ0 ~ IRQ63 Priority Control Register
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR2 NVIC_IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4n_0 PRI_4n_1 PRI_4n_2 PRI_4n_3

PRI_4n_0 : Priority of IRQ_4n+0\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 4 - 7 (4 bit)
access : read-write

PRI_4n_1 : Priority of IRQ_4n+1\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 12 - 15 (4 bit)
access : read-write

PRI_4n_2 : Priority of IRQ_4n+2\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 20 - 23 (4 bit)
access : read-write

PRI_4n_3 : Priority of IRQ_4n+3\n'0' denotes the highest priority and '15' denotes the lowest priority
bits : 28 - 31 (4 bit)
access : read-write


NVIC_ISER2 (ISER2)

IRQ0 ~ IRQ63 Set-enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER2 NVIC_ISER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt Disabled

1 : 1

Interrupt Enabled

End of enumeration elements list.


NVIC_ICER1 (ICER1)

IRQ0 ~ IRQ63 Clear-enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER1 NVIC_ICER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt Disabled

1 : 1

Interrupt Disabled.\nInterrupt Enabled

End of enumeration elements list.


NVIC_ICER2 (ICER2)

IRQ0 ~ IRQ63 Clear-enable Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER2 NVIC_ICER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALENA

CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nInterrupt Disabled

1 : 1

Interrupt Disabled.\nInterrupt Enabled

End of enumeration elements list.


STIR

Software Trigger Interrupt Registers
address_offset : 0xE00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STIR STIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt ID\nWrite to the STIR To Generate An Interrupt from Software\nWhen the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR\nInterrupt ID of the interrupt to trigger, in the range 0-63. For example, a value of 0x03 specifies interrupt IRQ3.
bits : 0 - 8 (9 bit)
access : read-write



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