TIMER0_CTL

TIMER0_CAP

TIMER0_EXTCTL

TIMER0_EINTSTS

TIMER1_CTL

TIMER1_CMP

TIMER1_INTSTS

TIMER1_CNT

TIMER1_CAP

TIMER1_EXTCTL

TIMER1_EINTSTS

TIMER0_CMP

TIMER0_INTSTS

TIMER0_CNT

PSC : Prescale Counter
bits : 0 - 7 (8 bit)
access : read-write

TRGSSEL : Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGPWM : Trigger PWM Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEADC : Trigger EADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger EADC.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TGLPINSEL : Toggle-output Pin Select
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Wake-up Function Enable Bit\nIf this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXTCNTEN : Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSTS : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RSTCNT : Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : Timer Counting Mode Select
bits : 27 - 28 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN : Timer Interrupt Enable Bit\nNote: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTEN : Timer Counting Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ICEDEBUG : ICE Debug Mode Acknowledge Disable (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDAT : Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only

CNTPHASE : Timer External Count Phase
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEDGE : Timer External Capture Pin Edge Detect
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPEN : Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPFUNCS : Capture Function Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIEN : Timer External Capture Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPDBEN : Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNTDBEN : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled, the edge detection of Tx pin is detected with de-bounce circuit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF : Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.\nNote2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.
bits : 0 - 23 (24 bit)
access : read-write

TIF : Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TWKF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CNT : Timer Data Register\nIf EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .\nIf EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.
bits : 0 - 23 (24 bit)
access : read-only