PWM

CTRLDn : Center Re-load\nEach bit n controls the corresponding PWM channel n.\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the center point of a period.
bits : 0 - 5 (6 bit)
access : read-write

WINLDENn : Window Load Enable Bit\nEach bit n controls the corresponding PWM channel n.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit

1 : 1

PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success

End of enumeration elements list.

IMMLDENn : Immediately Load Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: If IMMLDENn Enabled, WINLDENn and CTRLDn will be invalid.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

PERIOD will load to PBUF at the end point of each period. CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit

1 : 1

PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT

End of enumeration elements list.

GROUPEN : Group Function Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

The output waveform of each PWM channel are independent

#1 : 1

Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1

End of enumeration elements list.

DBGHALT : ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode. \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode counter halt Disabled

#1 : 1

ICE debug mode counter halt Enabled

End of enumeration elements list.

DBGTRIOFF : ICE Debug Mode Acknowledge Disable (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

ICE debug mode acknowledgement effects PWM output

#1 : 1

ICE debug mode acknowledgement disabled

End of enumeration elements list.

PWM_CLKSRC

PWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECLKSRC0 : PWM_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWMx_CLK, x denotes 0 or 1

#001 : 1

TIMER0 overflow

#010 : 2

TIMER1 overflow

#011 : 3

TIMER2 overflow

#100 : 4

TIMER3 overflow

End of enumeration elements list.

ECLKSRC2 : PWM_CH23 External Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWMx_CLK, x denotes 0 or 1

#001 : 1

TIMER0 overflow

#010 : 2

TIMER1 overflow

#011 : 3

TIMER2 overflow

#100 : 4

TIMER3 overflow

End of enumeration elements list.

ECLKSRC4 : PWM_CH45 External Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#000 : 0

PWMx_CLK, x denotes 0 or 1

#001 : 1

TIMER0 overflow

#010 : 2

TIMER1 overflow

#011 : 3

TIMER2 overflow

#100 : 4

TIMER3 overflow

End of enumeration elements list.

PWM_FTCMPDAT0_1

PWM Free Trigger Compare Register 0
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTCMP : PWM Free Trigger Compare Register\nFTCMP use to compare with even CNTR to trigger EADC. FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write

PWM_FTCMPDAT2_3

PWM Free Trigger Compare Register 2
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FTCMPDAT4_5

PWM Free Trigger Compare Register 4
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_SSCTL

PWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSENn : PWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN). Each bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM synchronous start function Disabled

1 : 1

PWM synchronous start function Enabled

End of enumeration elements list.

PWM_SSTRG

PWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CNTSEN : PWM Counter Synchronous Start Enable Bit (Write Only)\nPMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.\nNote: This bit only present in PWM0_BA.
bits : 0 - 0 (1 bit)
access : write-only

PWM_STATUS

PWM Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTMAXFn : Time-base Counter Equal to 0xFFFF Latched Flag\nEach bit n controls the corresponding PWM channel n.\nNote: Write 1 to clear this bit.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

The time-base counter never reached its maximum value 0xFFFF

1 : 1

The time-base counter reached its maximum value

End of enumeration elements list.

SYNCINFn : Input Synchronization Latched Flag\nEach bit n controls the corresponding PWM channel n.
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

0 : 0

No SYNC_IN event has occurred

1 : 1

An SYNC_IN event has occurred, software can write 1 to clear this bit

End of enumeration elements list.

ADCTRGFn : EADC Start of Conversion Flag\nEach bit n controls the corresponding PWM channel n.\nNote: Write 1 to clear this bit.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

No EADC start of conversion trigger event has occurred

1 : 1

An EADC start of conversion trigger event has occurred

End of enumeration elements list.

PWM_CLKPSC0_1

PWM Clock Pre-scale Register 0
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKPSC : PWM Counter Clock Pre-scale \nThe clock of PWM counter is decided by clock prescaler. Each PWM pair share one PWM counter clock prescaler. The clock of PWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write

PWM_CLKPSC2_3

PWM Clock Pre-scale Register 2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CLKPSC4_5

PWM Clock Pre-scale Register 4
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNTEN

PWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTENn : PWM Counter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM Counter and clock prescaler Stop Running

1 : 1

PWM Counter and clock prescaler Start Running

End of enumeration elements list.

PWM_CAPINEN

PWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPINENn : Capture Input Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM Channel capture input path Disabled. The input of PWM channel capture function is always regarded as 0

1 : 1

PWM Channel capture input path Enabled. The input of PWM channel capture function comes from correlative multifunction pin

End of enumeration elements list.

PWM_CAPCTL

PWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPENn : Capture Function Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated

1 : 1

Capture function Enabled. Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)

End of enumeration elements list.

CAPINVn : Capture Inverter Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture source inverter Disabled

1 : 1

Capture source inverter Enabled. Reverse the input signal from GPIO

End of enumeration elements list.

RCRLDENn : Rising Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Rising capture reload counter Disabled

1 : 1

Rising capture reload counter Enabled

End of enumeration elements list.

FCRLDENn : Falling Capture Reload Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0 : 0

Falling capture reload counter Disabled

1 : 1

Falling capture reload counter Enabled

End of enumeration elements list.

PWM_CAPSTS

PWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CRLIFOVn : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clears the corresponding CRLIF.
bits : 0 - 5 (6 bit)
access : read-only

CFLIFOVn : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1. Each bit n controls the corresponding PWM channel n.\nNote: This bit will be cleared automatically when user clears the corresponding CFLIF.
bits : 8 - 13 (6 bit)
access : read-only

PWM_RCAPDAT0

PWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCAPDAT : PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only

PWM_FCAPDAT0

PWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FCAPDAT : PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the PWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only

PWM_RCAPDAT1

PWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT1

PWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT2

PWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT2

PWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT3

PWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT3

PWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT4

PWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT4

PWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_RCAPDAT5

PWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FCAPDAT5

PWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PDMACTL

PWM PDMA Control Register
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHEN0_1 : Channel 0/1 PDMA Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 0/1 PDMA function Disabled

#1 : 1

Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory

End of enumeration elements list.

CAPMOD0_1 : Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer
bits : 1 - 2 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved.

#01 : 1

PWM_RCAPDAT0/1

#10 : 2

PWM_FCAPDAT0/1

#11 : 3

Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1

End of enumeration elements list.

CAPORD0_1 : Capture Channel 0/1 Rising/Falling Order
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_FCAPDAT0/1 is the first captured data to memory

#1 : 1

PWM_RCAPDAT0/1 is the first captured data to memory

End of enumeration elements list.

CHSEL0_1 : Select Channel 0/1 to Do PDMA Transfer
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel0

#1 : 1

Channel1

End of enumeration elements list.

CHEN2_3 : Channel 2/3 PDMA Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 2/3 PDMA function Disabled

#1 : 1

Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory

End of enumeration elements list.

CAPMOD2_3 : Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved.

#01 : 1

PWM_RCAPDAT2/3

#10 : 2

PWM_FCAPDAT2/3

#11 : 3

Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3

End of enumeration elements list.

CAPORD2_3 : Capture Channel 2/3 Rising/Falling Order
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_FCAPDAT2/3 is the first captured data to memory

#1 : 1

PWM_RCAPDAT2/3 is the first captured data to memory

End of enumeration elements list.

CHSEL2_3 : Select Channel 2/3 to Do PDMA Transfer
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel2

#1 : 1

Channel3

End of enumeration elements list.

CHEN4_5 : Channel 4/5 PDMA Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel 4/5 PDMA function Disabled

#1 : 1

Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory

End of enumeration elements list.

CAPMOD4_5 : Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer
bits : 17 - 18 (2 bit)
access : read-write

Enumeration:

#00 : 0

Reserved.

#01 : 1

PWM_RCAPDAT4/5

#10 : 2

PWM_FCAPDAT4/5

#11 : 3

Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5

End of enumeration elements list.

CAPORD4_5 : Capture Channel 4/5 Rising/Falling Order
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_FCAPDAT4/5 is the first captured data to memory

#1 : 1

PWM_RCAPDAT4/5 is the first captured data to memory

End of enumeration elements list.

CHSEL4_5 : Select Channel 4/5 to Do PDMA Transfer
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

Channel4

#1 : 1

Channel5

End of enumeration elements list.

PWM_CNTCLR

PWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTCLRn : Clear PWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

No effect

1 : 1

Clear 16-bit PWM counter to 0000H

End of enumeration elements list.

PWM_PDMACAP0_1

PWM Capture Channel 01 PDMA Register
address_offset : 0x240 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CAPBUF : PWM Capture PDMA Register (Read Only)\nThis register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.
bits : 0 - 15 (16 bit)
access : read-only

PWM_PDMACAP2_3

PWM Capture Channel 23 PDMA Register
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PDMACAP4_5

PWM Capture Channel 45 PDMA Register
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CAPIEN

PWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CAPRIENn : PWM Capture Rising Latch Interrupt Enable Bit\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture rising edge latch interrupt Disabled

1 : 1

Capture rising edge latch interrupt Enabled

End of enumeration elements list.

CAPFIENn : PWM Capture Falling Latch Interrupt Enable Bit\nEach bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

Capture falling edge latch interrupt Disabled

1 : 1

Capture falling edge latch interrupt Enabled

End of enumeration elements list.

PWM_CAPIF

PWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRLIFn : PWM Capture Rising Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

No capture rising latch condition happened

1 : 1

Capture rising latch condition happened, this flag will be set to high

End of enumeration elements list.

CFLIFn : PWM Capture Falling Latch Interrupt Flag\nThis bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.\nNote: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

No capture falling latch condition happened

1 : 1

Capture falling latch condition happened, this flag will be set to high

End of enumeration elements list.

PWM_LOAD

PWM Load Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOADn : Re-load PWM Comparator Register (CMPDAT) Control Bit\nThis bit is software write, hardware clear when current PWM period end. Each bit n controls the corresponding PWM channel n.\nWrite Operation:
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

No effect.\nNo load window is set

1 : 1

Set load window of window loading mode.\nLoad window is set

End of enumeration elements list.

PWM_PERIOD0

PWM Period Register 0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PERIOD : PWM Period Register\nUp-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.\nDown-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
bits : 0 - 15 (16 bit)
access : read-write

PWM_PBUF0

PWM PERIOD0 Buffer
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PBUF : PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only

PWM_PBUF1

PWM PERIOD1 Buffer
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PBUF2

PWM PERIOD2 Buffer
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PBUF3

PWM PERIOD3 Buffer
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PBUF4

PWM PERIOD4 Buffer
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PBUF5

PWM PERIOD5 Buffer
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPBUF0

PWM CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CMPBUF : PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only

PWM_CMPBUF1

PWM CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPBUF2

PWM CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPBUF3

PWM CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPBUF4

PWM CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPBUF5

PWM CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD1

PWM Period Register 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FTCBUF0_1

PWM FTCMPDAT0_1 Buffer
address_offset : 0x340 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FTCMPBUF : PWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMPDAT active register.
bits : 0 - 15 (16 bit)
access : read-only

PWM_FTCBUF2_3

PWM FTCMPDAT2_3 Buffer
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FTCBUF4_5

PWM FTCMPDAT4_5 Buffer
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_FTCI

PWM FTCMPDAT Indicator Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTCMUn : PWM FTCMPDAT Up Indicator
bits : 0 - 2 (3 bit)
access : read-write

FTCMDn : PWM FTCMPDAT Down Indicator
bits : 8 - 10 (3 bit)
access : read-write

PWM_PERIOD2

PWM Period Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD3

PWM Period Register 3
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CTL1

PWM Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNTTYPEn : PWM Counter Behavior Type\nEach bit n controls corresponding PWM channel n.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

00 : 0

Up counter type (supports in capture mode)

01 : 1

Down count type (supports in capture mode)

10 : 10

Up-down counter type

11 : 11

Reserved.

End of enumeration elements list.

CNTMODEn : PWM Counter Mode\nEach bit n controls the corresponding PWM channel n.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Auto-reload mode

1 : 1

One-shot mode

End of enumeration elements list.

OUTMODEn : PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : 0

PWM independent mode

1 : 1

PWM complementary mode

End of enumeration elements list.

PWM_PERIOD4

PWM Period Register 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PERIOD5

PWM Period Register 5
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT0

PWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMP : PWM Comparator Register\nCMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC.\nIn independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write

PWM_CMPDAT1

PWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT2

PWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT3

PWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT4

PWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CMPDAT5

PWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_DTCTL0_1

PWM Dead-time Control Register 0
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTCNT : Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write

DTEN : Dead-time Insertion for PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) Enable Bit (Write Protect)\nDead-time insertion is only active when this pair of complementary PWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Dead-time insertion on the pin pair Disabled

#1 : 1

Dead-time insertion on the pin pair Enabled

End of enumeration elements list.

DTCKSEL : Dead-time Clock Select (Write Protect)\nNote: This register is write protected. Refer to REGWRPROT register.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Dead-time clock source from PWM_CLK

#1 : 1

Dead-time clock source from prescaler output

End of enumeration elements list.

PWM_DTCTL2_3

PWM Dead-time Control Register 2
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_DTCTL4_5

PWM Dead-time Control Register 4
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_SYNC

PWM Synchronization Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHSENn : SYNC Phase Enable Bit\nEach bit n controls corresponding PWM channel n.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : 0

PWM counter load PHS value Disabled

1 : 1

PWM counter load PHS value Enabled

End of enumeration elements list.

SINSRCn : PWM0_SYNC_IN Source Selection\nEach bit n controls corresponding PWM channel n.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

00 : 0

Synchronize source from SYNC_IN or SWSYNC

01 : 1

Counter equal to 0

10 : 10

Counter equal to PWM_CMPDATm, m denotes 1, 3, 5

11 : 11

SYNC_OUT will not be generated

End of enumeration elements list.

SNFLTEN : PWM0_SYNC_IN Noise Filter Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter of input pin PWM0_SYNC_IN Disabled

#1 : 1

Noise filter of input pin PWM0_SYNC_IN Enabled

End of enumeration elements list.

SFLTCSEL : SYNC Edge Detector Filter Clock Selection
bits : 17 - 19 (3 bit)
access : read-write

Enumeration:

#000 : 0

Filter clock = HCLK

#001 : 1

Filter clock = HCLK/2

#010 : 2

Filter clock = HCLK/4

#011 : 3

Filter clock = HCLK/8

#100 : 4

Filter clock = HCLK/16

#101 : 5

Filter clock = HCLK/32

#110 : 6

Filter clock = HCLK/64

#111 : 7

Filter clock = HCLK/128

End of enumeration elements list.

SFLTCNT : SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector.
bits : 20 - 22 (3 bit)
access : read-write

SINPINV : SYNC Input Pin Inverse
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

The state of pin SYNC is passed to the positive edge detector

#1 : 1

The inversed state of pin SYNC is passed to the positive edge detector

End of enumeration elements list.

PHSDIRn : PWM Phase Direction Control\nEach bit n controls corresponding PWM channel n.
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : 0

Control PWM counter count decrement after synchronizing

1 : 1

Control PWM counter count increment after synchronizing

End of enumeration elements list.

PWM_PHS0_1

PWM Counter Phase Register 0
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHS : PWM Synchronous Start Phase Bits\nPHS determines the PWM synchronous start phase value. These bits only use in synchronous function.
bits : 0 - 15 (16 bit)
access : read-write

PWM_PHS2_3

PWM Counter Phase Register 2
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_PHS4_5

PWM Counter Phase Register 4
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT0

PWM Counter Register 0
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CNT : PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only

DIRF : PWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

Counter is Down count

#1 : 1

Counter is UP count

End of enumeration elements list.

PWM_CNT1

PWM Counter Register 1
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT2

PWM Counter Register 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT3

PWM Counter Register 3
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT4

PWM Counter Register 4
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_CNT5

PWM Counter Register 5
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_WGCTL0

PWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZPCTLn : PWM Zero Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to zero.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM zero point output Low

10 : 10

PWM zero point output High

11 : 11

PWM zero point output Toggle

End of enumeration elements list.

PRDPCTLn : PWM Period (Center) Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter count to (PERIODn+1).\nNote: This bit is center point control when PWM counter operating in up-down counter type.
bits : 16 - 27 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM period (center) point output Low

10 : 10

PWM period (center) point output High

11 : 11

PWM period (center) point output Toggle

End of enumeration elements list.

PWM_WGCTL1

PWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMPUCTLn : PWM Compare Up Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter up count to CMPDAT.\nNote: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 11 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM compare up point output Low

10 : 10

PWM compare up point output High

11 : 11

PWM compare up point output Toggle

End of enumeration elements list.

CMPDCTLn : PWM Compare Down Point Control\nEach bit n controls the corresponding PWM channel n.\nPWM can control output level when PWM counter down count to CMPDAT.\nNote: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 27 (12 bit)
access : read-write

Enumeration:

00 : 0

Do nothing

01 : 1

PWM compare down point output Low

10 : 10

PWM compare down point output High

11 : 11

PWM compare down point output Toggle

End of enumeration elements list.

PWM_MSKEN

PWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSKENn : PWM Mask Enable Bits\nEach bit n controls the corresponding PWM channel n.\nThe PWM output signal will be masked when this bit is enabled. The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM output signal is non-masked

1 : 1

PWM output signal is masked and output MSKDATn data

End of enumeration elements list.

PWM_MSK

PWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSKDATn : PWM Mask Data Bit\nThis data bit control the state of PWMn output pin, if corresponding mask function is enabled. Each bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Output logic low to PWMn

1 : 1

Output logic high to PWMn

End of enumeration elements list.

PWM_SWSYNC

PWM Software Control Synchronization Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWSYNCn : Software SYNC Function\nEach bit n controls corresponding PWM channel n.\nWhen SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.
bits : 0 - 2 (3 bit)
access : read-write

PWM_BNF

PWM Brake Noise Filter Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRK0NFEN : PWM Brake 0 Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter of PWM Brake 0 Disabled

#1 : 1

Noise filter of PWM Brake 0 Enabled

End of enumeration elements list.

BRK0NFSEL : Brake 0 Edge Detector Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#000 : 0

Filter clock = HCLK

#001 : 1

Filter clock = HCLK/2

#010 : 2

Filter clock = HCLK/4

#011 : 3

Filter clock = HCLK/8

#100 : 4

Filter clock = HCLK/16

#101 : 5

Filter clock = HCLK/32

#110 : 6

Filter clock = HCLK/64

#111 : 7

Filter clock = HCLK/128

End of enumeration elements list.

BRK0FCNT : Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
bits : 4 - 6 (3 bit)
access : read-write

BRK0PINV : Brake 0 Pin Inverse
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

The state of pin PWMx_BRAKE0 is passed to the negative edge detector

#1 : 1

The inversed state of pin PWMx_BRAKE10 is passed to the negative edge detector

End of enumeration elements list.

BRK1NFEN : PWM Brake 1 Noise Filter Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Noise filter of PWM Brake 1 Disabled

#1 : 1

Noise filter of PWM Brake 1 Enabled

End of enumeration elements list.

BRK1NFSEL : Brake 1 Edge Detector Filter Clock Selection
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

#000 : 0

Filter clock = HCLK

#001 : 1

Filter clock = HCLK/2

#010 : 2

Filter clock = HCLK/4

#011 : 3

Filter clock = HCLK/8

#100 : 4

Filter clock = HCLK/16

#101 : 5

Filter clock = HCLK/32

#110 : 6

Filter clock = HCLK/64

#111 : 7

Filter clock = HCLK/128

End of enumeration elements list.

BRK1FCNT : Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
bits : 12 - 14 (3 bit)
access : read-write

BRK1PINV : Brake 1 Pin Inverse
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

The state of pin PWMx_BRAKE1 is passed to the negative edge detector

#1 : 1

The inversed state of pin PWMx_BRAKE1 is passed to the negative edge detector

End of enumeration elements list.

BK0SRC : Brake 0 Pin Source Select\nFor PWM0 setting:
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake 0 pin source come from PWM0_BRAKE0.\nReserved

#1 : 1

Reserved.\nBrake 0 pin source come from PWM0_BRAKE0

End of enumeration elements list.

BK1SRC : Brake 1 Pin Source Select\nFor PWM0 setting:
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake 1 pin source come from PWM0_BRAKE1.\nBrake 1 pin source come from PWM1_BRAKE1

#1 : 1

Brake 1 pin source come from PWM1_BRAKE1.\nBrake 1 pin source come from PWM0_BRAKE1

End of enumeration elements list.

PWM_FAILBRK

PWM System Fail Brake Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSSBRKEN : Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake Function triggered by CSS detection Disabled

#1 : 1

Brake Function triggered by CSS detection Enabled

End of enumeration elements list.

BODBRKEN : Brown-out Detection Trigger PWM Brake Function 0 Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake Function triggered by BOD Disabled

#1 : 1

Brake Function triggered by BOD Enabled

End of enumeration elements list.

CORBRKEN : Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Brake Function triggered by Core lockup detection Disabled

#1 : 1

Brake Function triggered by Core lockup detection Enabled

End of enumeration elements list.

PWM_BRKCTL0_1

PWM Brake Edge Detect Control Register 0
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKP0EEN : PWMx_BRAKE0 Pin As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

BKP0 pin as edge-detect brake source Disabled

#1 : 1

BKP0 pin as edge-detect brake source Enabled

End of enumeration elements list.

BRKP1EEN : PWMx_BRAKE1 Pin As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

BKP1 pin as edge-detect brake source Disabled

#1 : 1

BKP1 pin as edge-detect brake source Enabled

End of enumeration elements list.

SYSEBEN : System Fail As Edge-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

System Fail condition as edge-detect brake source Disabled

#1 : 1

System Fail condition as edge-detect brake source Enabled

End of enumeration elements list.

BRKP0LEN : BKP0 Pin As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_BRAKE0 pin as level-detect brake source Disabled

#1 : 1

PWMx_BRAKE0 pin as level-detect brake source Enabled

End of enumeration elements list.

BRKP1LEN : BKP1 Pin As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWMx_BRAKE1 pin as level-detect brake source Disabled

#1 : 1

PWMx_BRAKE1 pin as level-detect brake source Enabled

End of enumeration elements list.

SYSLBEN : System Fail As Level-detect Brake Source Enable Bit (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

System Fail condition as level-detect brake source Disabled

#1 : 1

System Fail condition as level-detect brake source Enabled

End of enumeration elements list.

BRKAEVEN : PWM Brake Action Select for Even Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

#00 : 0

PWM even channel level-detect brake function not affect channel output

#01 : 1

PWM even channel output tri-state when level-detect brake happened

#10 : 2

PWM even channel output low level when level-detect brake happened

#11 : 3

PWM even channel output high level when level-detect brake happened

End of enumeration elements list.

BRKAODD : PWM Brake Action Select for Odd Channel (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

#00 : 0

PWM odd channel level-detect brake function not affect channel output

#01 : 1

PWM odd channel output tri-state when level-detect brake happened

#10 : 2

PWM odd channel output low level when level-detect brake happened

#11 : 3

PWM odd channel output high level when level-detect brake happened

End of enumeration elements list.

PWM_BRKCTL2_3

PWM Brake Edge Detect Control Register 2
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_BRKCTL4_5

PWM Brake Edge Detect Control Register 4
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM_POLCTL

PWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PINVn : PWM PIN Polar Inverse Control Bits\nThe register controls polarity state of PWM output. Each bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM output polar inverse Disabled

1 : 1

PWM output polar inverse Enabled

End of enumeration elements list.

PWM_POEN

PWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POENn : PWM Pin Output Enable Bits\nEach bit n controls the corresponding PWM channel n.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

PWM pin at tri-state

1 : 1

PWM pin in output mode

End of enumeration elements list.

PWM_SWBRK

PWM Software Brake Control Register
address_offset : 0xDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

BRKETRGn : PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : write-only

BRKLTRGn : PWM Level Brake Software Trigger (Write Only) (Write Protect)\nEach bit n controls the corresponding PWM pair n.\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register. \nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 10 (3 bit)
access : write-only

PWM_INTEN0

PWM Interrupt Enable Register 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZIENn : PWM Zero Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: Odd channels will read always 0 at complementary mode.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0 : 0

Zero point interrupt Disabled

1 : 1

Zero point interrupt Enabled

End of enumeration elements list.

IFAIEN0_1 : PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag accumulator interrupt Disabled

#1 : 1

Interrupt Flag accumulator interrupt Enabled

End of enumeration elements list.

PIENn : PWM Period Point Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 8 - 13 (6 bit)
access : read-write

Enumeration:

0 : 0

Period point interrupt Disabled

1 : 1

Period point interrupt Enabled

End of enumeration elements list.

IFAIEN2_3 : PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag accumulator interrupt Disabled

#1 : 1

Interrupt Flag accumulator interrupt Enabled

End of enumeration elements list.

CMPUIENn : PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write

Enumeration:

0 : 0

Compare up count interrupt Disabled

1 : 1

Compare up count interrupt Enabled

End of enumeration elements list.

IFAIEN4_5 : PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

Interrupt Flag accumulator interrupt Disabled

#1 : 1

Interrupt Flag accumulator interrupt Enabled

End of enumeration elements list.

CMPDIENn : PWM Compare Down Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 29 (6 bit)
access : read-write

Enumeration:

0 : 0

Compare down count interrupt Disabled

1 : 1

Compare down count interrupt Enabled

End of enumeration elements list.

PWM_INTEN1

PWM Interrupt Enable Register 1
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKEIEN0_1 : PWM Edge-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge-detect Brake interrupt for channel0/1 Disabled

#1 : 1

Edge-detect Brake interrupt for channel0/1 Enabled

End of enumeration elements list.

BRKEIEN2_3 : PWM Edge-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge-detect Brake interrupt for channel2/3 Disabled

#1 : 1

Edge-detect Brake interrupt for channel2/3 Enabled

End of enumeration elements list.

BRKEIEN4_5 : PWM Edge-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Edge-detect Brake interrupt for channel4/5 Disabled

#1 : 1

Edge-detect Brake interrupt for channel4/5 Enabled

End of enumeration elements list.

BRKLIEN0_1 : PWM Level-detect Brake Interrupt Enable Bit for Channel0/1 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level-detect Brake interrupt for channel0/1 Disabled

#1 : 1

Level-detect Brake interrupt for channel0/1 Enabled

End of enumeration elements list.

BRKLIEN2_3 : PWM Level-detect Brake Interrupt Enable Bit for Channel2/3 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level-detect Brake interrupt for channel2/3 Disabled

#1 : 1

Level-detect Brake interrupt for channel2/3 Enabled

End of enumeration elements list.

BRKLIEN4_5 : PWM Level-detect Brake Interrupt Enable Bit for Channel4/5 (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

Level-detect Brake interrupt for channel4/5 Disabled

#1 : 1

Level-detect Brake interrupt for channel4/5 Enabled

End of enumeration elements list.

PWM_INTSTS0

PWM Interrupt Flag Register 0
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ZIFn : PWM Zero Point Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nThis bit is set by hardware when PWM counter reaches 0; software can write 1 to clear this bit to 0.
bits : 0 - 5 (6 bit)
access : read-write

IFAIF0_1 : PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write

PIFn : PWM Period Point Interrupt Flag\nThis bit is set by hardware when PWM counter reaches PWM_PERIODn; software can write 1 to clear this bit to 0. Each bit n controls the corresponding PWM channel n.
bits : 8 - 13 (6 bit)
access : read-write

IFAIF2_3 : PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
bits : 15 - 15 (1 bit)
access : read-write

CMPUIFn : PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it. Each bit n controls the corresponding PWM channel n.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.\nNote2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
bits : 16 - 21 (6 bit)
access : read-write

IFAIF4_5 : PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
bits : 23 - 23 (1 bit)
access : read-write

CMPDIFn : PWM Compare Down Count Interrupt Flag\nEach bit n controls the corresponding PWM channel n.\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.\nNote2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.
bits : 24 - 29 (6 bit)
access : read-write

PWM_INTSTS1

PWM Interrupt Flag Register 1
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRKEIF0 : PWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel0 edge-detect brake event do not happened

#1 : 1

When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF1 : PWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel1 edge-detect brake event do not happened

#1 : 1

When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF2 : PWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel2 edge-detect brake event do not happened

#1 : 1

When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF3 : PWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel3 edge-detect brake event do not happened

#1 : 1

When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF4 : PWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel4 edge-detect brake event do not happened

#1 : 1

When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKEIF5 : PWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel5 edge-detect brake event do not happened

#1 : 1

When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF0 : PWM Channel0 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel0 level-detect brake event do not happened

#1 : 1

When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF1 : PWM Channel1 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel1 level-detect brake event do not happened

#1 : 1

When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF2 : PWM Channel2 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel2 level-detect brake event do not happened

#1 : 1

When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF3 : PWM Channel3 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel3 level-detect brake event do not happened

#1 : 1

When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF4 : PWM Channel4 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel4 level-detect brake event do not happened

#1 : 1

When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKLIF5 : PWM Channel5 Level-detect Brake Interrupt Flag (Write Protect)\nNote: This register is write protected. Refer to SYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel5 level-detect brake event do not happened

#1 : 1

When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear

End of enumeration elements list.

BRKESTS0 : PWM Channel0 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel0 edge-detect brake state is released

#1 : 1

When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state

End of enumeration elements list.

BRKESTS1 : PWM Channel1 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel1 edge-detect brake state is released

#1 : 1

When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state

End of enumeration elements list.

BRKESTS2 : PWM Channel2 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel2 edge-detect brake state is released

#1 : 1

When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state

End of enumeration elements list.

BRKESTS3 : PWM Channel3 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel3 edge-detect brake state is released

#1 : 1

When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state

End of enumeration elements list.

BRKESTS4 : PWM Channel4 Edge-detect Brake Status\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel4 edge-detect brake state is released

#1 : 1

When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state

End of enumeration elements list.

BRKESTS5 : PWM Channel5 Edge-detect Brake Status
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM channel5 edge-detect brake state is released

#1 : 1

When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state

End of enumeration elements list.

BRKLSTS0 : PWM Channel0 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 24 - 24 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM channel0 level-detect brake state is released

#1 : 1

When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state

End of enumeration elements list.

BRKLSTS1 : PWM Channel1 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 25 - 25 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM channel1 level-detect brake state is released

#1 : 1

When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state

End of enumeration elements list.

BRKLSTS2 : PWM Channel2 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 26 - 26 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM channel2 level-detect brake state is released

#1 : 1

When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state

End of enumeration elements list.

BRKLSTS3 : PWM Channel3 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 27 - 27 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM channel3 level-detect brake state is released

#1 : 1

When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state

End of enumeration elements list.

BRKLSTS4 : PWM Channel4 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM channel4 level-detect brake state is released

#1 : 1

When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state

End of enumeration elements list.

BRKLSTS5 : PWM Channel5 Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, PWM will release brake state until current PWM period finished. The PWM waveform will start output from next full PWM period.
bits : 29 - 29 (1 bit)
access : read-only

Enumeration:

#0 : 0

PWM channel5 level-detect brake state is released

#1 : 1

When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state

End of enumeration elements list.

PWM_IFA

PWM Interrupt Flag Accumulator Register
address_offset : 0xF0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFCNT0_1 : PWM_CH0 and PWM_CH1 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt. \nIFAIF0_1 (PWM_INTSTS0[7]) will be set in every IFCNT0_1+1 times of PWM period.
bits : 0 - 3 (4 bit)
access : read-write

IFSEL0_1 : PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Source Select
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#000 : 0

CNT equal to Zero in channel 0

#001 : 1

CNT equal to PERIOD in channel 0

#010 : 2

CNT equal to CMPU in channel 0

#011 : 3

CNT equal to CMPD in channel 0

#100 : 4

CNT equal to Zero in channel 1

#101 : 5

CNT equal to PERIOD in channel 1

#110 : 6

CNT equal to CMPU in channel 1

#111 : 7

CNT equal to CMPD in channel 1

End of enumeration elements list.

IFAEN0_1 : PWM_CH0 and PWM_CH1 Interrupt Flag Accumulator Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH0 and PWM_CH1 interrupt flag accumulator Disabled

#1 : 1

PWM_CH0 and PWM_CH1 interrupt flag accumulator Enabled

End of enumeration elements list.

IFCNT2_3 : PWM_CH2 and PWM_CH3 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt. \nIFAIF2_3 (PWM_INTSTS0[15]) will be set in every IFCNT2_3+1 times of PWM period.
bits : 8 - 11 (4 bit)
access : read-write

IFSEL2_3 : PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Source Select
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#000 : 0

CNT equal to Zero in channel 2

#001 : 1

CNT equal to PERIOD in channel 2

#010 : 2

CNT equal to CMPU in channel 2

#011 : 3

CNT equal to CMPD in channel 2

#100 : 4

CNT equal to Zero in channel 3

#101 : 5

CNT equal to PERIOD in channel 3

#110 : 6

CNT equal to CMPU in channel 3

#111 : 7

CNT equal to CMPD in channel 3

End of enumeration elements list.

IFAEN2_3 : PWM_CH2 and PWM_CH3 Interrupt Flag Accumulator Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH2 and PWM_CH3 interrupt flag accumulator Disabled

#1 : 1

PWM_CH2 and PWM_CH3 interrupt flag accumulator Enabled

End of enumeration elements list.

IFCNT4_5 : PWM_CH4 and PWM_CH5 Interrupt Flag Counter\nThe register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt. \nIFAIF4_5 (PWM_INTSTS0[23]) will be set in every IFCNT4_5+1 times of PWM period.
bits : 16 - 19 (4 bit)
access : read-write

IFSEL4_5 : PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Source Select
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#000 : 0

CNT equal to Zero in channel 4

#001 : 1

CNT equal to PERIOD in channel 4

#010 : 2

CNT equal to CMPU in channel 4

#011 : 3

CNT equal to CMPD in channel 4

#100 : 4

CNT equal to Zero in channel 5

#101 : 5

CNT equal to PERIOD in channel 5

#110 : 6

CNT equal to CMPU in channel 5

#111 : 7

CNT equal to CMPD in channel 5

End of enumeration elements list.

IFAEN4_5 : PWM_CH4 and PWM_CH5 Interrupt Flag Accumulator Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH4 and PWM_CH5 interrupt flag accumulator Disabled

#1 : 1

PWM_CH4 and PWM_CH5 interrupt flag accumulator Enabled

End of enumeration elements list.

PWM_EADCTS0

PWM Trigger EADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL0 : PWM_CH0 Trigger EADC Source Select
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM_CH0 zero point

#0001 : 1

PWM_CH0 period point

#0010 : 2

PWM_CH0 zero or period point

#0011 : 3

PWM_CH0 up-count CMPDAT point

#0100 : 4

PWM_CH0 down-count CMPDAT point

#0101 : 5

PWM_CH1 zero point

#0110 : 6

PWM_CH1 period point

#0111 : 7

PWM_CH1 zero or period point

#1000 : 8

PWM_CH1 up-count CMPDAT point

#1001 : 9

PWM_CH1 down-count CMPDAT point

#1010 : 10

PWM_CH0 up-count free CMPDAT point

#1011 : 11

PWM_CH0 down-count free CMPDAT point

#1100 : 12

PWM_CH2 up-count free CMPDAT point

#1101 : 13

PWM_CH2 down-count free CMPDAT point

#1110 : 14

PWM_CH4 up-count free CMPDAT point

#1111 : 15

PWM_CH4 down-count free CMPDAT point

End of enumeration elements list.

TRGEN0 : PWM_CH0 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH0 Trigger EADC Disabled

#1 : 1

PWM_CH0 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL1 : PWM_CH1 Trigger EADC Source Select
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM_CH0 zero point

#0001 : 1

PWM_CH0 period point

#0010 : 2

PWM_CH0 zero or period point

#0011 : 3

PWM_CH0 up-count CMPDAT point

#0100 : 4

PWM_CH0 down-count CMPDAT point

#0101 : 5

PWM_CH1 zero point

#0110 : 6

PWM_CH1 period point

#0111 : 7

PWM_CH1 zero or period point

#1000 : 8

PWM_CH1 up-count CMPDAT point

#1001 : 9

PWM_CH1 down-count CMPDAT point

#1010 : 10

PWM_CH0 up-count free CMPDAT point

#1011 : 11

PWM_CH0 down-count free CMPDAT point

#1100 : 12

PWM_CH2 up-count free CMPDAT point

#1101 : 13

PWM_CH2 down-count free CMPDAT point

#1110 : 14

PWM_CH4 up-count free CMPDAT point

#1111 : 15

PWM_CH4 down-count free CMPDAT point

End of enumeration elements list.

TRGEN1 : PWM_CH1 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH1 Trigger EADC Disabled

#1 : 1

PWM_CH1 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL2 : PWM_CH2 Trigger EADC Source Select
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM_CH2 zero point

#0001 : 1

PWM_CH2 period point

#0010 : 2

PWM_CH2 zero or period point

#0011 : 3

PWM_CH2 up-count CMPDAT point

#0100 : 4

PWM_CH2 down-count CMPDAT point

#0101 : 5

PWM_CH3 zero point

#0110 : 6

PWM_CH3 period point

#0111 : 7

PWM_CH3 zero or period point

#1000 : 8

PWM_CH3 up-count CMPDAT point

#1001 : 9

PWM_CH3 down-count CMPDAT point

#1010 : 10

PWM_CH0 up-count free CMPDAT point

#1011 : 11

PWM_CH0 down-count free CMPDAT point

#1100 : 12

PWM_CH2 up-count free CMPDAT point

#1101 : 13

PWM_CH2 down-count free CMPDAT point

#1110 : 14

PWM_CH4 up-count free CMPDAT point

#1111 : 15

PWM_CH4 down-count free CMPDAT point

End of enumeration elements list.

TRGEN2 : PWM_CH2 Trigger EADC Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH2 Trigger EADC Disabled

#1 : 1

PWM_CH2 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL3 : PWM_CH3 Trigger EADC Source Select
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM_CH2 zero point

#0001 : 1

PWM_CH2 period point

#0010 : 2

PWM_CH2 zero or period point

#0011 : 3

PWM_CH2 up-count CMPDAT point

#0100 : 4

PWM_CH2 down-count CMPDAT point

#0101 : 5

PWM_CH3 zero point

#0110 : 6

PWM_CH3 period point

#0111 : 7

PWM_CH3 zero or period point

#1000 : 8

PWM_CH3 up-count CMPDAT point

#1001 : 9

PWM_CH3 down-count CMPDAT point

#1010 : 10

PWM_CH0 up-count free CMPDAT point

#1011 : 11

PWM_CH0 down-count free CMPDAT point

#1100 : 12

PWM_CH2 up-count free CMPDAT point

#1101 : 13

PWM_CH2 down-count free CMPDAT point

#1110 : 14

PWM_CH4 up-count free CMPDAT point

#1111 : 15

PWM_CH4 down-count free CMPDAT point

End of enumeration elements list.

TRGEN3 : PWM_CH3 Trigger EADC Enable Bit
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH3 Trigger EADC Disabled

#1 : 1

PWM_CH3 Trigger EADC Enabled

End of enumeration elements list.

PWM_EADCTS1

PWM Trigger EADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRGSEL4 : PWM_CH4 Trigger EADC Source Select
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM_CH4 zero point

#0001 : 1

PWM_CH4 period point

#0010 : 2

PWM_CH4 zero or period point

#0011 : 3

PWM_CH4 up-count CMPDAT point

#0100 : 4

PWM_CH4 down-count CMPDAT point

#0101 : 5

PWM_CH5 zero point

#0110 : 6

PWM_CH5 period point

#0111 : 7

PWM_CH5 zero or period point

#1000 : 8

PWM_CH5 up-count CMPDAT point

#1001 : 9

PWM_CH5 down-count CMPDAT point

#1010 : 10

PWM_CH0 up-count free CMPDAT point

#1011 : 11

PWM_CH0 down-count free CMPDAT point

#1100 : 12

PWM_CH2 up-count free CMPDAT point

#1101 : 13

PWM_CH2 down-count free CMPDAT point

#1110 : 14

PWM_CH4 up-count free CMPDAT point

#1111 : 15

PWM_CH4 down-count free CMPDAT point

End of enumeration elements list.

TRGEN4 : PWM_CH4 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH4 Trigger EADC Disabled

#1 : 1

PWM_CH4 Trigger EADC Enabled

End of enumeration elements list.

TRGSEL5 : PWM_CH5 Trigger EADC Source Select
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

#0000 : 0

PWM_CH4 zero point

#0001 : 1

PWM_CH4 period point

#0010 : 2

PWM_CH4 zero or period point

#0011 : 3

PWM_CH4 up-count CMPDAT point

#0100 : 4

PWM_CH4 down-count CMPDAT point

#0101 : 5

PWM_CH5 zero point

#0110 : 6

PWM_CH5 period point

#0111 : 7

PWM_CH5 zero or period point

#1000 : 8

PWM_CH5 up-count CMPDAT point

#1001 : 9

PWM_CH5 down-count CMPDAT point

#1010 : 10

PWM_CH0 up-count free CMPDAT point

#1011 : 11

PWM_CH0 down-count free CMPDAT point

#1100 : 12

PWM_CH2 up-count free CMPDAT point

#1101 : 13

PWM_CH2 down-count free CMPDAT point

#1110 : 14

PWM_CH4 up-count free CMPDAT point

#1111 : 15

PWM_CH4 down-count free CMPDAT point

End of enumeration elements list.

TRGEN5 : PWM_CH5 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

#0 : 0

PWM_CH5 Trigger EADC Disabled

#1 : 1

PWM_CH5 Trigger EADC Enabled

End of enumeration elements list.

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ChipSelect

PWM

Peripheral Memory Blocks

Registers

PWM_CTL0

PWM_CLKSRC

PWM_FTCMPDAT0_1

PWM_FTCMPDAT2_3

PWM_FTCMPDAT4_5

PWM_SSCTL

PWM_SSTRG

PWM_STATUS

PWM_CLKPSC0_1

PWM_CLKPSC2_3

PWM_CLKPSC4_5

PWM_CNTEN

PWM_CAPINEN

PWM_CAPCTL

PWM_CAPSTS

PWM_RCAPDAT0

PWM_FCAPDAT0

PWM_RCAPDAT1

PWM_FCAPDAT1

PWM_RCAPDAT2

PWM_FCAPDAT2

PWM_RCAPDAT3

PWM_FCAPDAT3

PWM_RCAPDAT4

PWM_FCAPDAT4

PWM_RCAPDAT5

PWM_FCAPDAT5

PWM_PDMACTL

PWM_CNTCLR

PWM_PDMACAP0_1

PWM_PDMACAP2_3

PWM_PDMACAP4_5

PWM_CAPIEN

PWM_CAPIF

PWM_LOAD

PWM_PERIOD0

PWM_PBUF0

PWM_PBUF1

PWM_PBUF2

PWM_PBUF3

PWM_PBUF4

PWM_PBUF5

PWM_CMPBUF0

PWM_CMPBUF1

PWM_CMPBUF2

PWM_CMPBUF3

PWM_CMPBUF4

PWM_CMPBUF5

PWM_PERIOD1

PWM_FTCBUF0_1

PWM_FTCBUF2_3

PWM_FTCBUF4_5

PWM_FTCI

PWM_PERIOD2

PWM_PERIOD3

PWM_CTL1

PWM_PERIOD4

PWM_PERIOD5

PWM_CMPDAT0

PWM_CMPDAT1

PWM_CMPDAT2

PWM_CMPDAT3

PWM_CMPDAT4

PWM_CMPDAT5

PWM_DTCTL0_1

PWM_DTCTL2_3

PWM_DTCTL4_5

PWM_SYNC

PWM_PHS0_1

PWM_PHS2_3

PWM_PHS4_5

PWM_CNT0

PWM_CNT1

PWM_CNT2

PWM_CNT3

PWM_CNT4