Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x500 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection : not protected
USB Device Interrupt Enable Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSIEN : Bus Event Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BUS event interrupt Disabled
#1 : 1
BUS event interrupt Enabled
End of enumeration elements list.
USBIEN : USB Event Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB event interrupt Disabled
#1 : 1
USB event interrupt Enabled
End of enumeration elements list.
VBDETIEN : VBUS Detection Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
VBUS detection Interrupt Disabled
#1 : 1
VBUS detection Interrupt Enabled
End of enumeration elements list.
NEVWKIEN : USB No-event-wake-up Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No-event-wake-up Interrupt Disabled
#1 : 1
No-event-wake-up Interrupt Enabled
End of enumeration elements list.
WKEN : Wake-up Function Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB wake-up function Disabled
#1 : 1
USB wake-up function Enabled
End of enumeration elements list.
INNAKEN : Active NAK Function and Its Status in IN Token
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
When device responds NAK after receiving IN token, IN NAK status will not be updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted
#1 : 1
IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event will be asserted, when the device responds NAK after receiving IN token
End of enumeration elements list.
USB Device Bus Status and Attribution Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBRST : USB Reset Status\nNote: This bit is read only.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus no reset
#1 : 1
Bus reset when SE0 (single-ended 0) more than 2.5us
End of enumeration elements list.
SUSPEND : Suspend Status\nNote: This bit is read only.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bus no suspend
#1 : 1
Bus idle more than 3 ms, either cable is plugged off or host is sleeping
End of enumeration elements list.
RESUME : Resume Status\nNote: This bit is read only.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus resume
#1 : 1
Resume from suspend
End of enumeration elements list.
TOUT : Time-out Status\nNote: This bit is read only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No time-out
#1 : 1
No Bus response more than 18 bits time
End of enumeration elements list.
PHYEN : PHY Transceiver Function Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PHY transceiver function Disabled
#1 : 1
PHY transceiver function Enabled
End of enumeration elements list.
RWAKEUP : Remote Wake-up
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Release the USB bus from K state
#1 : 1
Force USB bus to K (USB_D+ low and USB_D- high) state, used for remote wake-up
End of enumeration elements list.
USBEN : USB Controller Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Controller Disabled
#1 : 1
USB Controller Enabled
End of enumeration elements list.
DPPUEN : Pull-up Resistor on USB_DP Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Pull-up resistor in USB_D+ bus Disabled
#1 : 1
Pull-up resistor in USB_D+ bus Active
End of enumeration elements list.
PWRDN : Power-down PHY Transceiver, Low Active
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down related circuits of PHY transceiver
#1 : 1
Turn-on related circuits of PHY transceiver
End of enumeration elements list.
BYTEM : CPU Access USB SRAM Size Mode Selection
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word mode: The size of the transfer from CPU to USB SRAM can be Word only
#1 : 1
Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only
End of enumeration elements list.
USB Device VBUS Detection Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VBUSDET : Device VBUS Detection
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Controller is not attached to the USB host
#1 : 1
Controller is attached to the USB host
End of enumeration elements list.
USB Setup Token Buffer Segmentation Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STBUFSEG : SETUP Token Buffer Segmentation\nIt is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is\nUSBD_SRAM address + {STBUFSEG, 3'b000} \nNote: It is used for SETUP token only.
bits : 3 - 8 (6 bit)
access : read-write
USB Device Interrupt Event Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSIF : BUS Interrupt Status\nThe BUS event means that there is one of the suspense or the resume function in the bus.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No BUS event occurred
#1 : 1
Bus event occurred; check USBD_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USBD_INTSTS[0]
End of enumeration elements list.
USBIF : USB Event Interrupt Status\nThe USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN or ISO OUT events in the bus.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No USB event occurred
#1 : 1
USB event occurred, check EPSTS0~5[2:0] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[1] or EPSTS0~7 and SETUP (USBD_INTSTS[31])
End of enumeration elements list.
VBDETIF : VBUS Detection Interrupt Status
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
There is not attached/detached event in the USB
#1 : 1
There is attached/detached event in the USB bus and it is cleared by write 1 to USBD_INTSTS[2]
End of enumeration elements list.
NEVWKIF : No-event-wake-up Interrupt Status
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
NEVWK event does not occur
#1 : 1
No-event-wake-up event occurred, cleared by write 1 to USBD_INTSTS[3]
End of enumeration elements list.
EPEVT0 : Endpoint 0's USB Event Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 0
#1 : 1
USB event occurred on Endpoint 0, check USBD_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[16] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT1 : Endpoint 1's USB Event Status
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 1
#1 : 1
USB event occurred on Endpoint 1, check USBD_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[17] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT2 : Endpoint 2's USB Event Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 2
#1 : 1
USB event occurred on Endpoint 2, check USBD_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[18] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT3 : Endpoint 3's USB Event Status
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 3
#1 : 1
USB event occurred on Endpoint 3, check USBD_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[19] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT4 : Endpoint 4's USB Event Status
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 4
#1 : 1
USB event occurred on Endpoint 4, check USBD_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[20] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT5 : Endpoint 5's USB Event Status
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 5
#1 : 1
USB event occurred on Endpoint 5, check USBD_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[21] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT6 : Endpoint 6's USB Event Status
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 6
#1 : 1
USB event occurred on Endpoint 6, check USBD_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[22] or USBD_INTSTS[1]
End of enumeration elements list.
EPEVT7 : Endpoint 7's USB Event Status
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in endpoint 7
#1 : 1
USB event occurred on Endpoint 7, check USBD_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USBD_INTSTS[23] or USBD_INTSTS[1]
End of enumeration elements list.
SETUP : Setup Event Status
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Setup event
#1 : 1
Setup event occurred, cleared by write 1 to USBD_INTSTS[31]
End of enumeration elements list.
USB Endpoint 0 Buffer Segmentation Register
address_offset : 0x500 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEG : Endpoint Buffer Segmentation\nIt is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is\nUSBD_SRAM address + {BUFSEG[8:3], 3'b000}\nRefer to the section 6.17.5.7 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write
USB Endpoint 0 Maximal Payload Register
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPLD : Maximal Payload\nDefine the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted out IN token or received in OUT token.\n(1) When the register is written by CPU, \nFor IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.\nFor OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.\n(2) When the register is read by CPU,\nFor IN token, the value of MXPLD is indicated by the data length be transmitted to host\nFor OUT token, the value of MXPLD is indicated the actual data length received from host.\nNote: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write
USB Endpoint 0 Configuration Register
address_offset : 0x508 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNUM : Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint
bits : 0 - 3 (4 bit)
access : read-write
ISOCH : Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshaking.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Isochronous endpoint
#1 : 1
Isochronous endpoint
End of enumeration elements list.
STATE : Endpoint State
bits : 5 - 6 (2 bit)
access : read-write
Enumeration:
#00 : 0
Endpoint Disabled
#01 : 1
Out endpoint
#10 : 2
IN endpoint
#11 : 3
Undefined
End of enumeration elements list.
DSQSYNC : Data Sequence Synchronization\nNote: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. hardware will toggle automatically in IN token base on the bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DATA0 PID
#1 : 1
DATA1 PID
End of enumeration elements list.
CSTALL : Clear STALL Response
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the device to clear the STALL handshake in setup stage
#1 : 1
Clear the device to response STALL handshake in setup stage
End of enumeration elements list.
USB Endpoint 0 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x50C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRRDY : Clear Ready\nWhen the USBD_MXPLDx register is set by user, it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start, users can set this bit to 1 to disable it and it is auto clear to 0.\nFor IN token\nThis bit is write 1 only and is always 0 when it is read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear the IN token had ready to transmit the data to USB host.\nClear the OUT token had ready to receive the data from USB host
End of enumeration elements list.
SSTALL : Set STALL
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable the device to response STALL
#1 : 1
Set the device to respond STALL automatically
End of enumeration elements list.
USB Endpoint 1 Buffer Segmentation Register
address_offset : 0x510 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 1 Maximal Payload Register
address_offset : 0x514 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 1 Configuration Register
address_offset : 0x518 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 1 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x51C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 2 Buffer Segmentation Register
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 2 Maximal Payload Register
address_offset : 0x524 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 2 Configuration Register
address_offset : 0x528 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 2 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x52C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 3 Buffer Segmentation Register
address_offset : 0x530 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 3 Maximal Payload Register
address_offset : 0x534 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 3 Configuration Register
address_offset : 0x538 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 3 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x53C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 4 Buffer Segmentation Register
address_offset : 0x540 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 4 Maximal Payload Register
address_offset : 0x544 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 4 Configuration Register
address_offset : 0x548 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 4 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x54C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 5 Buffer Segmentation Register
address_offset : 0x550 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 5 Maximal Payload Register
address_offset : 0x554 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 5 Configuration Register
address_offset : 0x558 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 5 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x55C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 6 Buffer Segmentation Register
address_offset : 0x560 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 6 Maximal Payload Register
address_offset : 0x564 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 6 Configuration Register
address_offset : 0x568 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 6 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x56C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 7 Buffer Segmentation Register
address_offset : 0x570 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 7 Maximal Payload Register
address_offset : 0x574 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 7 Configuration Register
address_offset : 0x578 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Endpoint 7 Set Stall and Clear In/Out Ready Control Register
address_offset : 0x57C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Device Function Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FADDR : USB Device Function Address
bits : 0 - 6 (7 bit)
access : read-write
USB Device Drive SE0 Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SE0 : Drive Single Ended Zero in USB Bus\nThe Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Normal operation
#1 : 1
Force USB PHY transceiver to drive SE0
End of enumeration elements list.
USB Device Endpoint Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OV : Overrun\nIt indicates that the received data is over the maximum payload number or not.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No overrun
#1 : 1
Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 bytes
End of enumeration elements list.
EPSTS0 : Endpoint 0 Status\nThese bits are used to indicate the current status of this endpoint
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS1 : Endpoint 1 Status\nThese bits are used to indicate the current status of this endpoint
bits : 11 - 13 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS2 : Endpoint 2 Status\nThese bits are used to indicate the current status of this endpoint
bits : 14 - 16 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS3 : Endpoint 3 Status\nThese bits are used to indicate the current status of this endpoint
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS4 : Endpoint 4 Status\nThese bits are used to indicate the current status of this endpoint
bits : 20 - 22 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS5 : Endpoint 5 Status\nThese bits are used to indicate the current status of this endpoint
bits : 23 - 25 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS6 : Endpoint 6 Status\nThese bits are used to indicate the current status of this endpoint
bits : 26 - 28 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
EPSTS7 : Endpoint 7 Status\nThese bits are used to indicate the current status of this endpoint
bits : 29 - 31 (3 bit)
access : read-only
Enumeration:
#000 : 0
In ACK
#001 : 1
In NAK
#010 : 2
Out Packet Data0 ACK
#011 : 3
Setup ACK
#110 : 6
Out Packet Data1 ACK
#111 : 7
Isochronous transfer end
End of enumeration elements list.
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