CLK_PWRCTL (PWRCTL)

CLK_CLKSEL0 (CLKSEL0)

CLK_CLKSEL1 (CLKSEL1)

CLK_CLKSEL2 (CLKSEL2)

CLK_CLKSEL3 (CLKSEL3)

CLK_CLKDIV0 (CLKDIV0)

CLK_CLKDIV1 (CLKDIV1)

CLK_CLKDIV2 (CLKDIV2)

CLK_CLKDIV3 (CLKDIV3)

CLK_CLKDIV4 (CLKDIV4)

CLK_PCLKDIV (PCLKDIV)

CLK_AHBCLK (AHBCLK)

CLK_PLLCTL (PLLCTL)

CLK_STATUS (STATUS)

CLK_CLKOCTL (CLKOCTL)

CLK_CLKDCTL (CLKDCTL)

CLK_CLKDSTS (CLKDSTS)

CLK_CDUPB (CDUPB)

CLK_CDLOWB (CDLOWB)

CLK_APBCLK0 (APBCLK0)

CLK_PMUCTL (PMUCTL)

CLK_PMUSTS (PMUSTS)

CLK_LDOCTL (LDOCTL)

CLK_SWKDBCTL (SWKDBCTL)

CLK_PASWKCTL (PASWKCTL)

CLK_PBSWKCTL (PBSWKCTL)

CLK_PCSWKCTL (PCSWKCTL)

CLK_PDSWKCTL (PDSWKCTL)

CLK_IOPDCTL (IOPDCTL)

CLK_APBCLK1 (APBCLK1)

HXTEN : HXT Enable Bit (Write Protect) The bit default value is set by Flash controller user configuration register CONFIG0 [26:24]. When the default clock source is from HXT, this bit is set to 1 automatically. Note: 1.This bit is write protected. Refer to the SYS_REGLCTL register. 2.When HXT is enabled, GPIO must be set as input mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTEN : LXT Enable Bit (Write Protect) Note: 1. This bit is write protected. Refer to the SYS_REGLCTL register. 2. When LXT is enabled, GPIO must be set as input mode.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRCEN : HIRC Enable Bit (Write Protect) Note:1.This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRCEN : LIRC Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDWKDLY : Enable the Wake-up Delay Counter (Write Protect) When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 256 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). Note: This bit is write protected. Refer to the SYS_REGLCTL register
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDWKIEN : Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\nNote1: The interrupt will occur when both PDWKIF and PDWKIEN are high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDWKIF : Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event', it indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred. Refer Power Modes and Wake-up Sources chapter.\nNote1: Write 1 to clear the bit to 0.\nNote2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
bits : 6 - 6 (1 bit)
access : read-write

PDEN : System Power-down Enable (Write Protect) When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set this bit again for next Power-down. In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTGAIN : HXT Gain Control Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled, crystal will consume more power than gain control off. \nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTSELTYP : HXT Crystal Type Select Bit (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTTBEN : HXT Crystal TURBO Mode (Write Protect)\nThis is a protected register. Please refer to open lock sequence to program it.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRCSTBS : HIRC Stable Count Select (Write Protect ) Others: Reserved Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC48MEN : HIRC48M Enable Bit (Write Protect) Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKSEL : HCLK Clock Source Selection (Write Protect)\nBefore clock switching, the related clock sources (both pre-select and new-select) must be turned on.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STCLKSEL : Cortex-M4F SysTick Clock Source Selection (Write Protect) Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 5 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBSEL : USB Clock Source Selection (Write Protect)
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCAPSEL : CCAP Engine Clock Source Selection (Write Protect)
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDH0SEL : SD0 Engine Clock Source Selection (Write Protect)
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDH1SEL : SD1 Engine Clock Source Selection (Write Protect)
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDTSEL : Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0SEL : TIMER0 Clock Source Selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1SEL : TIMER1 Clock Source Selection
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2SEL : TIMER2 Clock Source Selection
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3SEL : TIMER3 Clock Source Selection
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0SEL : UART0 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1SEL : UART1 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKOSEL : Clock Divider Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WWDTSEL : Window Watchdog Timer Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPWM0SEL : EPWM0 Clock Source Selection\nThe peripheral clock source of EPWM0 is defined by EPWM0SEL.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPWM1SEL : EPWM1 Clock Source Selection\nThe peripheral clock source of EPWM1 is defined by EPWM1SEL.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QSPI0SEL : QSPI0 Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0SEL : SPI0 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1SEL : SPI1 Clock Source Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWM0SEL : BPWM0 Clock Source Selection\nThe peripheral clock source of BPWM0 is defined by BPWM0SEL.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BPWM1SEL : BPWM1 Clock Source Selection\nThe peripheral clock source of BPWM1 is defined by BPWM1SEL.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2SEL : SPI2 Clock Source Selection
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI3SEL : SPI3 Clock Source Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC0SEL : SC0 Clock Source Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC1SEL : SC0 Clock Source Selection
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC2SEL : SC2 Clock Source Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCSEL : RTC Clock Source Selection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QSPI1SEL : QSPI1 Clock Source Selection
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S0SEL : I2S0 Clock Source Selection
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART6SEL : UART6 Clock Source Selection
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART7SEL : UART7 Clock Source Selection
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2SEL : UART2 Clock Source Selection
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART3SEL : UART3 Clock Source Selection
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4SEL : UART4 Clock Source Selection
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART5SEL : UART5 Clock Source Selection
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLKDIV : HCLK Clock Divide Number From HCLK Clock Source Note: If HCLK clock source frequency is PLL, HCLKDIV should not be 1. HCLK PLL/2
bits : 0 - 3 (4 bit)
access : read-write

USBDIV : USB Clock Divide Number From PLL Clock
bits : 4 - 7 (4 bit)
access : read-write

UART0DIV : UART0 Clock Divide Number From UART0 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

UART1DIV : UART1 Clock Divide Number From UART1 Clock Source
bits : 12 - 15 (4 bit)
access : read-write

EADCDIV : EADC Clock Divide Number From EADC Clock Source
bits : 16 - 23 (8 bit)
access : read-write

SDH0DIV : SD0 Clock Divide Number From SD0 Clock Source
bits : 24 - 31 (8 bit)
access : read-write

SC0DIV : SC0 Clock Divide Number From SC0 Clock Source
bits : 0 - 7 (8 bit)
access : read-write

SC1DIV : SC1 Clock Divide Number From SC1 Clock Source
bits : 8 - 15 (8 bit)
access : read-write

SC2DIV : SC2 Clock Divide Number From SC2 Clock Source
bits : 16 - 23 (8 bit)
access : read-write

I2S0DIV : I2S0 Clock Divide Number From I2S0 Clock Source
bits : 0 - 3 (4 bit)
access : read-write

EADC1DIV : EADC1 Clock Divide Number From EADC Clock Source
bits : 24 - 31 (8 bit)
access : read-write

CCAPDIV : Camera Capture Sensor Clock Divide Number From CCAP Clock Source
bits : 0 - 7 (8 bit)
access : read-write

VSENSEDIV : Video Pixel Clock Divide Number From CCAP Clock Source
bits : 8 - 15 (8 bit)
access : read-write

EMACDIV : Ethernet Clock Divide Number Form HCLK
bits : 16 - 23 (8 bit)
access : read-write

SDH1DIV : SD1 Clock Divide Number From SD1 Clock Source
bits : 24 - 31 (8 bit)
access : read-write

UART2DIV : UART2 Clock Divide Number From UART2 Clock Source
bits : 0 - 3 (4 bit)
access : read-write

UART3DIV : UART3 Clock Divide Number From UART3 Clock Source
bits : 4 - 7 (4 bit)
access : read-write

UART4DIV : UART4 Clock Divide Number From UART4 Clock Source
bits : 8 - 11 (4 bit)
access : read-write

UART5DIV : UART5 Clock Divide Number From UART5 Clock Source
bits : 12 - 15 (4 bit)
access : read-write

UART6DIV : UART6 Clock Divide Number From UART6 Clock Source
bits : 16 - 19 (4 bit)
access : read-write

UART7DIV : UART7 Clock Divide Number From UART7 Clock Source
bits : 20 - 23 (4 bit)
access : read-write

APB0DIV : APB0 Clock Divider APB0 clock can be divided from HCLK Others: Reserved. Note: PCLK must be less than 96 MHz.
bits : 0 - 2 (3 bit)
access : read-write

APB1DIV : APB1 Clock Divider APB1 clock can be divided from HCLK Others: Reserved. Note: PCLK must be less than 96 MHz.
bits : 4 - 6 (3 bit)
access : read-write

PDMACKEN : PDMA Controller Clock Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPCKEN : Flash ISP Controller Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EBICKEN : EBI Controller Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMACCKEN : Ethernet Controller Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDH0CKEN : SD0 Controller Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRCCKEN : CRC Generator Controller Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCAPCKEN : Camera Capture Interface Controller Clock Enable Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SENCKEN : Sensor Clock Enable Control
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSUSBDCKEN : HSUSB Device Clock Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRPTCKEN : Cryptographic Accelerator Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPIMCKEN : SPIM Controller Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FMCIDLE : Flash Memory Controller Clock Enable Bit in IDLE Mode
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBHCKEN : USB HOST Controller Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SDH1CKEN : SD1 Controller Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FBDIV : PLL Feedback Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 8 (9 bit)
access : read-write

INDIV : PLL Input Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 13 (5 bit)
access : read-write

OUTDIV : PLL Output Divider Control (Write Protect)\nRefer to the formulas below the table.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 14 - 15 (2 bit)
access : read-write

PD : Power-down Mode (Write Protect)\nIf set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BP : PLL Bypass Control (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OE : PLL OE (FOUT Enable) Pin Control (Write Protect) Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. Note 2: If HCLK is switched to PLL, OE(CLK_PLLCTL[18]) cannot be set to 1 to avoid clock stop.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLLSRC : PLL Source Clock Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STBSEL : PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BANDSEL : PLL Stable Counter Selection (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTSTB : HXT Clock Source Stable Flag (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LXTSTB : LXT Clock Source Stable Flag (Read Only)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLLSTB : Internal PLL Clock Source Stable Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIRCSTB : LIRC Clock Source Stable Flag (Read Only)
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRCSTB : HIRC Clock Source Stable Flag (Read Only)
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRC48MSTB : HIRC48M Clock Source Stable Flag (Read Only)
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKSFAIL : Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source. If switch target clock is stable, this bit will be set to 0. If switch target clock is not stable, this bit will be set to 1.\nNote: Write 1 to clear the bit to 0.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FREQSEL : Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write

CLKOEN : Clock Output Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIV1EN : Clock Output Divide One Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLK1HZEN : Clock Output 1Hz Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFDEN : HXT Clock Fail Detector Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFIEN : HXT Clock Fail Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTFDEN : LXT Clock Fail Detector Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTFIEN : LXT Clock Fail Interrupt Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFQDEN : HXT Clock Frequency Range Detector Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFQIEN : HXT Clock Frequency Range Detector Interrupt Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFIF : HXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXTFIF : LXT Clock Fail Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXTFQIF : HXT Clock Frequency Range Detector Interrupt Flag\nNote: Write 1 to clear the bit to 0.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UPERBD : HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write

LOWERBD : HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1.
bits : 0 - 9 (10 bit)
access : read-write

WDTCKEN : Watchdog Timer Clock Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCCKEN : Real-time-clock APB Interface Clock Enable Bit\nThis bit is used to control the RTC APB clock only. The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]). It can be selected to 32.768 kHz external low speed crystal or 10 kHz internal low speed RC oscillator (LIRC).
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0CKEN : Timer0 Clock Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1CKEN : Timer1 Clock Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2CKEN : Timer2 Clock Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3CKEN : Timer3 Clock Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKOCKEN : CLKO Clock Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP01CKEN : Analog Comparator 0/1 Clock Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0CKEN : I2C0 Clock Enable Bit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1CKEN : I2C1 Clock Enable Bit
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C2CKEN : I2C2 Clock Enable Bit
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QSPI0CKEN : QSPI0 Clock Enable Bit
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0CKEN : SPI0 Clock Enable Bit
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1CKEN : SPI1 Clock Enable Bit
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2CKEN : SPI2 Clock Enable Bit
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0CKEN : UART0 Clock Enable Bit
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1CKEN : UART1 Clock Enable Bit
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART2CKEN : UART2 Clock Enable Bit
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART3CKEN : UART3 Clock Enable Bit
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART4CKEN : UART4 Clock Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART5CKEN : UART5 Clock Enable Bit
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART6CKEN : UART6 Clock Enable Bit
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART7CKEN : UART7 Clock Enable Bit
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAN0CKEN : CAN0 Clock Enable Bit
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAN1CKEN : CAN1 Clock Enable Bit
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OTGCKEN : USB OTG Clock Enable Bit
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBDCKEN : USB Device Clock Enable Bit
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EADCCKEN : Enhanced Analog-digital-converter (EADC) Clock Enable Bit
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S0CKEN : I2S0 Clock Enable Bit
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSOTGCKEN : HSUSB OTG Clock Enable Bit
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMSEL : Power-down Mode Selection (Write Protect)\nThis is a protected bit. Please refer to open lock sequence to program it.\nThese bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPDHOLDEN : Deep-power-down Mode GPIO Hold Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRETSEL : SRAM Retention Range Select Bit (Write Protect) Select SRAM retention range when chip enter SPD mode. (M48xGC/M48xE8) Note: This bit is write protected. Refer to the SYS_REGLCTL register. Note: Chip may work in SPD mode abnormally, if not select SRAM retention size before enter SPD mode.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKTMREN : Wake-up Timer Enable Bit (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. Note: This bit is write protected. Refer to the SYS_REGLCTL register
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKTMRIS : Wake-up Timer Time-out Interval Select (Write Protect)\nThis is a protected bit. Please refer to open lock sequence to program it.\nThese bits control wake-up timer time-out interval when chip at DPD/SPD mode.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 12 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINEN : Wake-up Pin Enable Bit (Write Protect)\nThis is a protected bit. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINEN0 : Wake-up Pin0 Enable Bit (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. This is control register for GPC.0 to wake-up pin. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMPSPWK : ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect)\nThis is a protected bit. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTCWKEN : RTC Wake-up Enable Bit (Write Protect)\nThis is a protected bit. Please refer to open lock sequence to program it.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINEN1 : Wake-up Pin1 Enable Bit (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. This is control register for GPB.0 to wake-up pin. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINEN2 : Wake-up Pin2 Enable Bit (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. This is control register for GPB.2 to wake-up pin. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINEN3 : Wake-up Pin3 Enable Bit (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. This is control register for GPB.12 to wake-up pin. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPINEN4 : Wake-up Pin4 Enable Bit (Write Protect) This is a protected bit. Please refer to open lock sequence to program it. This is control register for GPF.6 to wake-up pin. Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PINWK : Pin Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). This flag is cleared when DPD mode is entered.
bits : 0 - 0 (1 bit)
access : read-only

PINWK0 : Pin0 Wake-up Flag (Read Only) This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). This flag is cleared when DPD mode is entered.
bits : 0 - 0 (1 bit)
access : read-only

TMRWK : Timer Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. This flag is cleared when DPD or SPD mode is entered.
bits : 1 - 1 (1 bit)
access : read-only

RTCWK : RTC Wake-up Flag (Read Only) This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. This flag is cleared when DPD or SPD mode is entered.
bits : 2 - 2 (1 bit)
access : read-only

PINWK1 : Pin1 Wake-up Flag (Read Only) This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). This flag is cleared when DPD mode is entered.
bits : 3 - 3 (1 bit)
access : read-only

PINWK2 : Pin2 Wake-up Flag (Read Only) This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). This flag is cleared when DPD mode is entered.
bits : 4 - 4 (1 bit)
access : read-only

PINWK3 : Pin3 Wake-up Flag (Read Only) This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). This flag is cleared when DPD mode is entered.
bits : 5 - 5 (1 bit)
access : read-only

PINWK4 : Pin4 Wake-up Flag (Read Only) This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). This flag is cleared when DPD mode is entered.
bits : 6 - 6 (1 bit)
access : read-only

GPAWK : GPA Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. This flag is cleared when SPD mode is entered.
bits : 8 - 8 (1 bit)
access : read-only

GPBWK : GPB Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins. This flag is cleared when SPD mode is entered.
bits : 9 - 9 (1 bit)
access : read-only

GPCWK : GPC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. This flag is cleared when SPD mode is entered.
bits : 10 - 10 (1 bit)
access : read-only

GPDWK : GPD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. This flag is cleared when SPD mode is entered.
bits : 11 - 11 (1 bit)
access : read-only

LVRWK : LVR Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened. This flag is cleared when SPD mode is entered.
bits : 12 - 12 (1 bit)
access : read-only

BODWK : BOD Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. This flag is cleared when SPD mode is entered.
bits : 13 - 13 (1 bit)
access : read-only

ACMPWK : ACMP Wake-up Flag (Read Only)\nThis flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition. This flag is cleared when SPD mode is entered.
bits : 14 - 14 (1 bit)
access : read-only

CLRWK : Clear Wake-up Flag
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DPDWKSEL : DPD Wake Up Time Select Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDBIASEN : Power-down Bias Enable Bit\nNote: This bit should set to 1 before chip enter power-down mode.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SWKDBCLKSEL : Standby Power-down Wake-up De-bounce Sampling Cycle Selection\nNote: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC).
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPSEL : GPA Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN : GPA Input Signal De-bounce Enable Bit The DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. The de-bounce clock source is the 10 kHz internal low speed RC oscillator. The de-bounce function is valid only for edgetriggered.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPSEL : GPB Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN : GPB Input Signal De-bounce Enable Bit The DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. The de-bounce clock source is the 10 kHz internal low speed RC oscillator. The de-bounce function is valid only for edgetriggered.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKEN : Standby Power-down Pin Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRWKEN : Pin Rising Edge Wake-up Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PFWKEN : Pin Falling Edge Wake-up Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKPSEL : GPC Standby Power-down Wake-up Pin Select
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN : GPC Input Signal De-bounce Enable Bit The DBEN bit is used to enable the de-bounce function for each corresponding IO. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. The de-bounce clock source is the 10 kHz internal low speed RC oscillator. Note: The de-bounce function is valid only for edgetriggered.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.