PDMA_CHCTL (CHCTL)

PDMA_PAUSE (PAUSE)

PDMA_SWREQ (SWREQ)

PDMA_TRGSTS (TRGSTS)

PDMA_PRISET (PRISET)

PDMA_PRICLR (PRICLR)

PDMA_INTEN (INTEN)

PDMA_INTSTS (INTSTS)

PDMA_ABTSTS (ABTSTS)

PDMA_TDSTS (TDSTS)

PDMA_ALIGN (ALIGN)

PDMA_TACTSTS (TACTSTS)

PDMA_TOUTPSC (TOUTPSC)

PDMA_TOUTEN (TOUTEN)

PDMA_TOUTIEN (TOUTIEN)

PDMA_SCATBA (SCATBA)

PDMA_TOC0_1 (TOC0_1)

PDMA_CHRST (CHRST)

PDMA_REQSEL0_3 (REQSEL0_3)

PDMA_REQSEL4_7 (REQSEL4_7)

PDMA_REQSEL8_11 (REQSEL8_11)

PDMA_REQSEL12_15 (REQSEL12_15)

PDMA_STC0 (STC0)

PDMA_ASOCTL0 (ASOCTL0)

PDMA_STC1 (STC1)

PDMA_ASOCTL1 (ASOCTL1)

PDMA_STC2 (STC2)

PDMA_ASOCTL2 (ASOCTL2)

PDMA_STC3 (STC3)

PDMA_ASOCTL3 (ASOCTL3)

PDMA_STC4 (STC4)

PDMA_ASOCTL4 (ASOCTL4)

PDMA_STC5 (STC5)

PDMA_ASOCTL5 (ASOCTL5)

PDMA_AICTL0 (AICTL0)

PDMA_RCNT0 (RCNT0)

PDMA_AICTL1 (AICTL1)

PDMA_RCNT1 (RCNT1)

CHEN0 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN5 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN6 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN7 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN8 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN9 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN10 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN11 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN12 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN13 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN14 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN15 : PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.\nNote: Setting the corresponding bit of PDMA_PAUSE or PDMA_CHRST register will also clear this bit.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PAUSE0 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE1 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE2 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE3 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE4 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE5 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE6 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE7 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE8 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE9 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE10 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE11 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE12 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE13 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE14 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

PAUSE15 : PDMA Channel n Transfer Pause Control (Write Only)
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ0 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ1 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ2 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ3 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ4 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ5 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ6 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ7 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ8 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ9 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ10 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ11 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ12 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ13 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ14 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

SWREQ15 : PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\nNote 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request or peripheral request.\nNote 2: If user does not enable corresponding PDMA channel, the software request will be ignored.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

REQSTS0 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS1 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS2 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS3 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS4 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS5 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS6 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS7 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS8 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS9 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS10 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS11 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS12 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS13 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS14 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQSTS15 : PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not, no matter request from software or peripheral. When PDMA controller finishes channel transfer, this bit will be cleared automatically. \nNote: If user pauses or resets each PDMA transfer by setting PDMA_PAUSE or PDMA_CHRST register respectively, this bit will be cleared automatically after finishing the current transfer.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FPRISET0 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET1 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET2 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET3 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET4 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET5 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET6 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET7 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET8 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET9 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET10 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET11 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET12 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET13 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET14 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRISET15 : PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPRICLR0 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 0 - 0 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR1 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 1 - 1 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR2 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 2 - 2 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR3 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 3 - 3 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR4 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 4 - 4 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR5 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 5 - 5 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR6 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR7 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 7 - 7 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR8 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 8 - 8 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR9 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 9 - 9 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR10 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 10 - 10 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR11 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 11 - 11 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR12 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 12 - 12 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR13 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 13 - 13 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR14 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 14 - 14 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

FPRICLR15 : PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority.
bits : 15 - 15 (1 bit)
access : write-only

Enumeration:

End of enumeration elements list.

INTEN0 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN1 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN2 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN3 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN4 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN5 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN6 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN7 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN8 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN9 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN10 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN11 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN12 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN13 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN14 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTEN15 : PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF : PDMA Read/Write Target Abort Interrupt Flag (Read Only) This bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TDIF : Transfer Done Interrupt Flag (Read Only) This bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ALIGNF : Transfer Alignment Interrupt Flag (Read Only)
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

REQTOF0 : Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0, user can write 1 to clear these bits.\nNote: Please disable time-out function before clear this bit.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQTOF1 : Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1, user can write 1 to clear these bits.\nNote: Please disable time-out function before clear this bit.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF0 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF1 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF2 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF3 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF4 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF5 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF6 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF7 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF8 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF9 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF10 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF11 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF12 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF13 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF14 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABTIF15 : PDMA Read/Write Target Abort Interrupt Status Flag This bit indicates which PDMA controller has target abort error User can write 1 to clear these bits. Note: If channel n target abort, REQSRCn should set0 to disable peripheral request.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF0 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF1 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF2 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF3 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF4 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF5 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF6 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF7 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF8 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF9 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF10 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF11 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF12 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF13 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF14 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDIF15 : Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN0 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN1 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN2 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN3 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN4 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN5 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN6 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN7 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN8 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN9 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN10 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN11 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN12 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN13 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN14 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ALIGN15 : Transfer Alignment Flag\nNote: Source address and destination address should be alignment.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXACTF0 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF1 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF2 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF3 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF4 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF5 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF6 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF7 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF8 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF9 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF10 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF11 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF12 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 12 - 12 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF13 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 13 - 13 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF14 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 14 - 14 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXACTF15 : Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active.
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOUTPSC0 : PDMA Channel 0 Time-out Clock Source Prescaler Bits
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTPSC1 : PDMA Channel 1 Time-out Clock Source Prescaler Bits
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTEN0 : PDMA Time-out Enable Bits
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTEN1 : PDMA Time-out Enable Bits
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTIEN0 : PDMA Time-out Interrupt Enable Bits
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TOUTIEN1 : PDMA Time-out Interrupt Enable Bits
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SCATBA : PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode, this is the base address for calculating the next link - list address. The next link address equation is \nNote: Only useful in Scatter-Gather mode.
bits : 16 - 31 (16 bit)
access : read-write

TOC0 : Time-out Counter for Channel 0\nThis controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock.
bits : 0 - 15 (16 bit)
access : read-write

TOC1 : Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock. The example of time-out period can refer TOC0 bit description.
bits : 16 - 31 (16 bit)
access : read-write

CHnRST : Channel n Reset\nNote: This function don't support stride mode.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSRC0 : Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.\nNote 1: A peripheral cannot be assigned to two channels at the same time.\nNote 2: This field is useless when transfer between memory and memory.
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REQSRC1 : Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 14 (7 bit)
access : read-write

REQSRC2 : Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 22 (7 bit)
access : read-write

REQSRC3 : Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 30 (7 bit)
access : read-write

REQSRC4 : Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 6 (7 bit)
access : read-write

REQSRC5 : Channel 5 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 14 (7 bit)
access : read-write

REQSRC6 : Channel 6 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 22 (7 bit)
access : read-write

REQSRC7 : Channel 7 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 30 (7 bit)
access : read-write

REQSRC8 : Channel 8 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 6 (7 bit)
access : read-write

REQSRC9 : Channel 9 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 14 (7 bit)
access : read-write

REQSRC10 : Channel 10 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 10. User can configure the peripheral setting by REQSRC10. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 22 (7 bit)
access : read-write

REQSRC11 : Channel 11 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 11. User can configure the peripheral setting by REQSRC11. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 30 (7 bit)
access : read-write

REQSRC12 : Channel 12 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 12. User can configure the peripheral setting by REQSRC12. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 0 - 6 (7 bit)
access : read-write

REQSRC13 : Channel 13 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 13. User can configure the peripheral setting by REQSRC13. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 8 - 14 (7 bit)
access : read-write

REQSRC14 : Channel 14 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 14. User can configure the peripheral setting by REQSRC14. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 16 - 22 (7 bit)
access : read-write

REQSRC15 : Channel 15 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 15. User can configure the peripheral setting by REQSRC15. \nNote: The channel configuration is the same as REQSRC0 field. Please refer to the explanation of REQSRC0.
bits : 24 - 30 (7 bit)
access : read-write

STC : PDMA Stride Transfer Count\nThe 16-bit register defines the stride transfer count of each row, the real transfer count is (STC + 1).
bits : 0 - 15 (16 bit)
access : read-write

SASOL : PDMA Source Address Stride Offset Length\nThe 16-bit register defines the source address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write

DASOL : PDMA Destination Address Stride Offset Length\nThe 16-bit register defines the destination address stride transfer offset count of each row.
bits : 16 - 31 (16 bit)
access : read-write