Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
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size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
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mem_usage : registers
protection : not protected
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size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xF4 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x130 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x150 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x160 Bytes (0x0)
size : 0x38 byte (0x0)
mem_usage : registers
protection : not protected
EPWM Control Register 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRLD0 : Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period.
bits : 0 - 0 (1 bit)
access : read-write
CTRLD1 : Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period.
bits : 1 - 1 (1 bit)
access : read-write
CTRLD2 : Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period.
bits : 2 - 2 (1 bit)
access : read-write
CTRLD3 : Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period.
bits : 3 - 3 (1 bit)
access : read-write
CTRLD4 : Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period.
bits : 4 - 4 (1 bit)
access : read-write
CTRLD5 : Center Re-load\nIn up-down counter type, PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the center point of a period.
bits : 5 - 5 (1 bit)
access : read-write
WINLDEN0 : Window Load Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN1 : Window Load Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN2 : Window Load Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN3 : Window Load Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN4 : Window Load Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
WINLDEN5 : Window Load Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point of each period when valid reload window is set. The valid reload window is set by software write 1 to EPWM_LOAD register and cleared by hardware after load success
End of enumeration elements list.
IMMLDEN0 : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP
End of enumeration elements list.
IMMLDEN1 : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP
End of enumeration elements list.
IMMLDEN2 : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP
End of enumeration elements list.
IMMLDEN3 : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP
End of enumeration elements list.
IMMLDEN4 : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP
End of enumeration elements list.
IMMLDEN5 : Immediately Load Enable Bits\nNote: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PERIOD will load to PBUF at the end point of each period. CMP will load to CMPBUF at the end point or center point of each period by setting CTRLD bit
#1 : 1
PERIOD/CMP will load to PBUF and CMPBUF immediately when software update PERIOD/CMP
End of enumeration elements list.
GROUPEN : Group Function Enable Bit
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
The output waveform of each EPWM channel are independent
#1 : 1
Unify the EPWM_CH2 and EPWM_CH4 to output the same waveform as EPWM_CH0 and unify the EPWM_CH3 and EPWM_CH5 to output the same waveform as EPWM_CH1
End of enumeration elements list.
DBGHALT : ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode.
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode counter halt Disabled
#1 : 1
ICE debug mode counter halt Enabled
End of enumeration elements list.
DBGTRIOFF : ICE Debug Mode Acknowledge Disable Bit (Write Protect)
EPWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement effects EPWM output
#1 : 1
ICE debug mode acknowledgement disabled
End of enumeration elements list.
EPWM Clock Source Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECLKSRC0 : EPWM_CH01 External Clock Source Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
EPWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
ECLKSRC2 : EPWM_CH23 External Clock Source Select
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
EPWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
ECLKSRC4 : EPWM_CH45 External Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#000 : 0
EPWMx_CLK, x denotes 0 or 1
#001 : 1
TIMER0 overflow
#010 : 2
TIMER1 overflow
#011 : 3
TIMER2 overflow
#100 : 4
TIMER3 overflow
End of enumeration elements list.
EPWM Free Trigger Compare Register 0/1
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTCMP : EPWM Free Trigger Compare Register
bits : 0 - 15 (16 bit)
access : read-write
EPWM Free Trigger Compare Register 2/3
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Free Trigger Compare Register 4/5
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Synchronous Start Control Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN0 : EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM synchronous start function Disabled
#1 : 1
EPWM synchronous start function Enabled
End of enumeration elements list.
SSEN1 : EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM synchronous start function Disabled
#1 : 1
EPWM synchronous start function Enabled
End of enumeration elements list.
SSEN2 : EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM synchronous start function Disabled
#1 : 1
EPWM synchronous start function Enabled
End of enumeration elements list.
SSEN3 : EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM synchronous start function Disabled
#1 : 1
EPWM synchronous start function Enabled
End of enumeration elements list.
SSEN4 : EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM synchronous start function Disabled
#1 : 1
EPWM synchronous start function Enabled
End of enumeration elements list.
SSEN5 : EPWM Synchronous Start Function Enable Bits\nWhen synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN).
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM synchronous start function Disabled
#1 : 1
EPWM synchronous start function Enabled
End of enumeration elements list.
SSRC : EPWM Synchronous Start Source Select Bits
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronous start source come from EPWM0
#01 : 1
Synchronous start source come from EPWM1
#10 : 2
Synchronous start source come from BPWM0
#11 : 3
Synchronous start source come from BPWM1
End of enumeration elements list.
EPWM Synchronous Start Trigger Register
address_offset : 0x114 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CNTSEN : EPWM Counter Synchronous Start Enable (Write Only)\nPMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled.
bits : 0 - 0 (1 bit)
access : write-only
EPWM Leading Edge Blanking Control Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBEN : EPWM Leading Edge Blanking Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Leading Edge Blanking Disabled
#1 : 1
EPWM Leading Edge Blanking Enabled
End of enumeration elements list.
SRCEN0 : EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled
#1 : 1
EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled
End of enumeration elements list.
SRCEN2 : EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled
#1 : 1
EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled
End of enumeration elements list.
SRCEN4 : EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled
#1 : 1
EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled
End of enumeration elements list.
TRGTYPE : EPWM Leading Edge Blanking Trigger Type
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : 0
When detect leading edge blanking source rising edge, blanking counter start counting
1 : 1
When detect leading edge blanking source falling edge, blanking counter start counting
2 : 2
When detect leading edge blanking source rising or falling edge, blanking counter start counting
3 : 3
Reserved.
End of enumeration elements list.
EPWM Leading Edge Blanking Counter Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEBCNT : EPWM Leading Edge Blanking Counter
bits : 0 - 8 (9 bit)
access : read-write
EPWM Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTMAXF0 : Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
CNTMAXF1 : Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
CNTMAXF2 : Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
CNTMAXF3 : Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
CNTMAXF4 : Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
CNTMAXF5 : Time-base Counter Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The time-base counter never reached its maximum value 0xFFFF
#1 : 1
The time-base counter reached its maximum value
End of enumeration elements list.
SYNCINF0 : Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SYNC_IN event has occurred
#1 : 1
A SYNC_IN event has occurred
End of enumeration elements list.
SYNCINF2 : Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SYNC_IN event has occurred
#1 : 1
A SYNC_IN event has occurred
End of enumeration elements list.
SYNCINF4 : Input Synchronization Latched Flag\nNote: This bit can be cleared by software writing 1.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SYNC_IN event has occurred
#1 : 1
A SYNC_IN event has occurred
End of enumeration elements list.
EADCTRGF0 : EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRGF1 : EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRGF2 : EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRGF3 : EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRGF4 : EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
EADCTRGF5 : EADC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No EADC start of conversion trigger event has occurred
#1 : 1
An EADC start of conversion trigger event has occurred
End of enumeration elements list.
DACTRGF : DAC Start of Conversion Flag\nNote: This bit can be cleared by software writing 1.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No DAC start of conversion trigger event has occurred
#1 : 1
A DAC start of conversion trigger event has occurred
End of enumeration elements list.
EPWM Interrupt Flag Accumulator Register 0
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFACNT : EPWM_CHn Interrupt Flag Counter\nThe register sets the count number which defines (IFACNT+1) times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt.\nEPWM flag will be set in every IFACNT[15:0] times of EPWM period.
bits : 0 - 15 (16 bit)
access : read-write
STPMOD : EPWM_CHn Accumulator Stop Mode Enable Bits
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CHn Stop Mode Disable
#1 : 1
EPWM_CHn Stop Mode Enable
End of enumeration elements list.
IFASEL : EPWM_CHn Interrupt Flag Accumulator Source Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
EPWM_CHn zero point
#01 : 1
EPWM_CHn period in channel n
#10 : 2
EPWM_CHn up-count compared point
#11 : 3
EPWM_CHn down-count compared point
End of enumeration elements list.
IFAEN : EPWM_CHn Interrupt Flag Accumulator Enable Bits
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CHn interrupt flag accumulator Disabled
#1 : 1
EPWM_CHn interrupt flag accumulator Enabled
End of enumeration elements list.
EPWM Interrupt Flag Accumulator Register 1
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Interrupt Flag Accumulator Register 2
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Interrupt Flag Accumulator Register 3
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Clock Prescale Register 0/1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKPSC : EPWM Counter Clock Prescale \nThe clock of EPWM counter is decided by clock prescaler. Each EPWM pair share one EPWM counter clock prescaler. The clock of EPWM counter is divided by (CLKPSC+ 1).
bits : 0 - 11 (12 bit)
access : read-write
EPWM Interrupt Flag Accumulator Register 4
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Interrupt Flag Accumulator Register 5
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Accumulator Interrupt Flag Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFAIF0 : EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
IFAIF1 : EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
IFAIF2 : EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
IFAIF3 : EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
IFAIF4 : EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
IFAIF5 : EPWM_CHn Interrupt Flag Accumulator Interrupt Flag\nFlag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
EPWM Accumulator Interrupt Enable Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IFAIEN0 : EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
IFAIEN1 : EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
IFAIEN2 : EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
IFAIEN3 : EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
IFAIEN4 : EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
IFAIEN5 : EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Flag accumulator interrupt Disabled
#1 : 1
Interrupt Flag accumulator interrupt Enabled
End of enumeration elements list.
EPWM Accumulator PDMA Control Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APDMAEN0 : Channel n Accumulator PDMA Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n PDMA function Disabled
#1 : 1
Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register
End of enumeration elements list.
APDMAEN1 : Channel n Accumulator PDMA Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n PDMA function Disabled
#1 : 1
Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register
End of enumeration elements list.
APDMAEN2 : Channel n Accumulator PDMA Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n PDMA function Disabled
#1 : 1
Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register
End of enumeration elements list.
APDMAEN3 : Channel n Accumulator PDMA Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n PDMA function Disabled
#1 : 1
Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register
End of enumeration elements list.
APDMAEN4 : Channel n Accumulator PDMA Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n PDMA function Disabled
#1 : 1
Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register
End of enumeration elements list.
APDMAEN5 : Channel n Accumulator PDMA Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel n PDMA function Disabled
#1 : 1
Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register
End of enumeration elements list.
EPWM Fault Detect Enable Register
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDEN0 : EPWM Fault Detect Function Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect function Disable
#1 : 1
Fault detect function Enable
End of enumeration elements list.
FDEN1 : EPWM Fault Detect Function Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect function Disable
#1 : 1
Fault detect function Enable
End of enumeration elements list.
FDEN2 : EPWM Fault Detect Function Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect function Disable
#1 : 1
Fault detect function Enable
End of enumeration elements list.
FDEN3 : EPWM Fault Detect Function Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect function Disable
#1 : 1
Fault detect function Enable
End of enumeration elements list.
FDEN4 : EPWM Fault Detect Function Enable Bit
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect function Disable
#1 : 1
Fault detect function Enable
End of enumeration elements list.
FDEN5 : EPWM Fault Detect Function Enable Bit
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect function Disable
#1 : 1
Fault detect function Enable
End of enumeration elements list.
FDODIS0 : EPWM Channel n Output Fault Detect Disable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM detect fault and output Enable
#1 : 1
EPWM detect fault and output Disable
End of enumeration elements list.
FDODIS1 : EPWM Channel n Output Fault Detect Disable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM detect fault and output Enable
#1 : 1
EPWM detect fault and output Disable
End of enumeration elements list.
FDODIS2 : EPWM Channel n Output Fault Detect Disable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM detect fault and output Enable
#1 : 1
EPWM detect fault and output Disable
End of enumeration elements list.
FDODIS3 : EPWM Channel n Output Fault Detect Disable Bit
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM detect fault and output Enable
#1 : 1
EPWM detect fault and output Disable
End of enumeration elements list.
FDODIS4 : EPWM Channel n Output Fault Detect Disable Bit
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM detect fault and output Enable
#1 : 1
EPWM detect fault and output Disable
End of enumeration elements list.
FDODIS5 : EPWM Channel n Output Fault Detect Disable Bit
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM detect fault and output Enable
#1 : 1
EPWM detect fault and output Disable
End of enumeration elements list.
FDCKS0 : EPWM Channel n Fault Detect Clock Source Select Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CLK, x denotes 0 or 1
#1 : 1
EPWMx_CLK divide by prescaler, x denotes 0 or 1
End of enumeration elements list.
FDCKS1 : EPWM Channel n Fault Detect Clock Source Select Bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CLK, x denotes 0 or 1
#1 : 1
EPWMx_CLK divide by prescaler, x denotes 0 or 1
End of enumeration elements list.
FDCKS2 : EPWM Channel n Fault Detect Clock Source Select Bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CLK, x denotes 0 or 1
#1 : 1
EPWMx_CLK divide by prescaler, x denotes 0 or 1
End of enumeration elements list.
FDCKS3 : EPWM Channel n Fault Detect Clock Source Select Bit
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CLK, x denotes 0 or 1
#1 : 1
EPWMx_CLK divide by prescaler, x denotes 0 or 1
End of enumeration elements list.
FDCKS4 : EPWM Channel n Fault Detect Clock Source Select Bit
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CLK, x denotes 0 or 1
#1 : 1
EPWMx_CLK divide by prescaler, x denotes 0 or 1
End of enumeration elements list.
FDCKS5 : EPWM Channel n Fault Detect Clock Source Select Bit
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CLK, x denotes 0 or 1
#1 : 1
EPWMx_CLK divide by prescaler, x denotes 0 or 1
End of enumeration elements list.
EPWM Fault Detect Control Register 0
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRMSKCNT : Transition Mask Counter\nThe fault detect result will be masked before counter count from 0 to TRMSKCNT.\n\nFDCKS is set to 0: \nMask time is EPWMx_CLK * (2^FDCKSEL) * (TRMSKCNT+2)\nFDCKS is set to 1: \nMask time EPWMx_CLK * CLKPSC * (2^FDCKSEL) * (TRMSKCNT+2)\n\nNote:\nCLKPSC (EPWM_CLKPSCn_m[11:0]) is 0:
bits : 0 - 6 (7 bit)
access : read-write
FDMSKEN : Fault Detect Mask Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect mask function Disable
#1 : 1
Fault detect mask function Enable
End of enumeration elements list.
DGSMPCYC : Deglitch Sampling Cycle
FDCKS is set to 0:
Sampling detect signal each EPWMx_CLK * (2^FDCKSEL) period and detect DGSMPCYC+1 times
FDCKS is set to 1:
Sampling detect signal each EPWMx_CLK * CLKPSC * (2^FDCKSEL) period and detect DGSMPCYC+1 times
Note:
CLKPSC (EPWM_CLKPSCn_m[11:0]) is 0:
bits : 16 - 18 (3 bit)
access : read-write
FDCKSEL : EPWM Channel Fault Detect Clock Select
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
FLT_CLK/1
#01 : 1
FLT_CLK/2
#10 : 2
FLT_CLK/4
#11 : 3
FLT_CLK/8
End of enumeration elements list.
FDDGEN : Fault Detect Deglitch Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fault detect deglitch function Disable
#1 : 1
Fault detect deglitch function Enable
End of enumeration elements list.
EPWM Fault Detect Control Register 1
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Fault Detect Control Register 2
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Fault Detect Control Register 3
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Fault Detect Control Register 4
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Fault Detect Control Register 5
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Fault Detect Interrupt Enable Register
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDIENn : EPWM Channel n Fault Detect Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel n Fault Detect Interrupt Disable
#1 : 1
EPWM Channel n Fault Detect Interrupt Enable
End of enumeration elements list.
EPWM Clock Prescale Register 2/3
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Fault Detect Interrupt Flag Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FDIFn : EPWM Channel n Fault Detect Interrupt Flag Bit\nFault Detect Interrupt Flag will be set when EPWM output short. Software can clear this bit by writing 1 to it.
bits : 0 - 5 (6 bit)
access : read-write
EPWM Trigger EADC Prescale Control Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSCEN0 : EPWM Trigger EADC Pre-scale Function Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Trigger EADC Pre-scale Function Disable
#1 : 1
EPWM Trigger EADC Pre-scale Function Enable
End of enumeration elements list.
PSCEN1 : EPWM Trigger EADC Pre-scale Function Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Trigger EADC Pre-scale Function Disable
#1 : 1
EPWM Trigger EADC Pre-scale Function Enable
End of enumeration elements list.
PSCEN2 : EPWM Trigger EADC Pre-scale Function Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Trigger EADC Pre-scale Function Disable
#1 : 1
EPWM Trigger EADC Pre-scale Function Enable
End of enumeration elements list.
PSCEN3 : EPWM Trigger EADC Pre-scale Function Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Trigger EADC Pre-scale Function Disable
#1 : 1
EPWM Trigger EADC Pre-scale Function Enable
End of enumeration elements list.
PSCEN4 : EPWM Trigger EADC Pre-scale Function Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Trigger EADC Pre-scale Function Disable
#1 : 1
EPWM Trigger EADC Pre-scale Function Enable
End of enumeration elements list.
PSCEN5 : EPWM Trigger EADC Pre-scale Function Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Trigger EADC Pre-scale Function Disable
#1 : 1
EPWM Trigger EADC Pre-scale Function Enable
End of enumeration elements list.
EPWM Trigger EADC Prescale Register 0
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADCPSC0 : EPWM Channel 0 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC0+1) times of EPWM_CH0 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF0.
bits : 0 - 3 (4 bit)
access : read-write
EADCPSC1 : EPWM Channel 1 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC1+1) times of EPWM_CH1 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF1.
bits : 8 - 11 (4 bit)
access : read-write
EADCPSC2 : EPWM Channel 2 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC2+1) times of EPWM_CH2 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF2.
bits : 16 - 19 (4 bit)
access : read-write
EADCPSC3 : EPWM Channel 3 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC3+1) times of EPWM_CH3 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF3.
bits : 24 - 27 (4 bit)
access : read-write
EPWM Trigger EADC Prescale Register 1
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADCPSC4 : EPWM Channel 4 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC4+1) times of EPWM_CH4 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF4.
bits : 0 - 3 (4 bit)
access : read-write
EADCPSC5 : EPWM Channel 5 Trigger EADC Prescale\nThe register sets the count number which defines (EADCPSC5+1) times of EPWM_CH5 trigger EADC event occurs to trigger EADC and set trigger EADC flag bit EADCTRGF5.
bits : 8 - 11 (4 bit)
access : read-write
EPWM Trigger EADC Prescale Counter Register 0
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSCNT0 : EPWM Trigger EADC Prescale Counter 0
User can monitor PSCNT0 to know the current value in 4-bit trigger EADC prescale counter.
Note1: user can write only when PSCEN0 is 0.
Note2: Write data limitation: PSCNT0 EADCPSC0.
bits : 0 - 3 (4 bit)
access : read-write
PSCNT1 : EPWM Trigger EADC Prescale Counter 1
User can monitor PSCNT1 to know the current value in 4-bit trigger EADC prescale counter.
Note1: user can write only when PSCEN1 is 0.
Note2: Write data limitation: PSCNT1 EADCPSC1.
bits : 8 - 11 (4 bit)
access : read-write
PSCNT2 : EPWM Trigger EADC Prescale Counter 2
User can monitor PSCNT2 to know the current value in 4-bit trigger EADC prescale counter.
Note1: user can write only when PSCEN2 is 0.
Note2: Write data limitation: PSCNT2 EADCPSC2.
bits : 16 - 19 (4 bit)
access : read-write
PSCNT3 : EPWM Trigger EADC Prescale Counter 3
User can monitor PSCNT3 to know the current value in 4-bit trigger EADC prescale counter.
Note1: user can write only when PSCEN3 is 0.
Note2: Write data limitation: PSCNT3 EADCPSC3.
bits : 24 - 27 (4 bit)
access : read-write
EPWM Trigger EADC Prescale Counter Register 1
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSCNT4 : EPWM Trigger EADC Prescale Counter 4
User can monitor PSCNT4 to know the current value in 4-bit trigger EADC prescale counter.
Note1: user can write only when PSCEN4 is 0.
Note2: Write data limitation: PSCNT4 EADCPSC4.
bits : 0 - 3 (4 bit)
access : read-write
PSCNT5 : EPWM Trigger EADC Prescale Counter 5
User can monitor PSCNT5 to know the current value in 4-bit trigger EADC prescale counter.
Note1: user can write only when PSCEN5 is 0.
Note2: Write data limitation: PSCNT5 EADCPSC5.
bits : 8 - 11 (4 bit)
access : read-write
EPWM Clock Prescale Register 4/5
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Enable Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN0 : EPWM Counter Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Counter and clock prescaler stop running
#1 : 1
EPWM Counter and clock prescaler start running
End of enumeration elements list.
CNTEN1 : EPWM Counter Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Counter and clock prescaler stop running
#1 : 1
EPWM Counter and clock prescaler start running
End of enumeration elements list.
CNTEN2 : EPWM Counter Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Counter and clock prescaler stop running
#1 : 1
EPWM Counter and clock prescaler start running
End of enumeration elements list.
CNTEN3 : EPWM Counter Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Counter and clock prescaler stop running
#1 : 1
EPWM Counter and clock prescaler start running
End of enumeration elements list.
CNTEN4 : EPWM Counter Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Counter and clock prescaler stop running
#1 : 1
EPWM Counter and clock prescaler start running
End of enumeration elements list.
CNTEN5 : EPWM Counter Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Counter and clock prescaler stop running
#1 : 1
EPWM Counter and clock prescaler start running
End of enumeration elements list.
EPWM Capture Input Enable Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPINEN0 : Capture Input Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0
#1 : 1
EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN1 : Capture Input Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0
#1 : 1
EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN2 : Capture Input Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0
#1 : 1
EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN3 : Capture Input Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0
#1 : 1
EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN4 : Capture Input Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0
#1 : 1
EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
CAPINEN5 : Capture Input Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Channel capture input path Disabled. The input of EPWM channel capture function is always regarded as 0
#1 : 1
EPWM Channel capture input path Enabled. The input of EPWM channel capture function comes from correlative multifunction pin
End of enumeration elements list.
EPWM Capture Control Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPEN0 : Capture Function Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated
#1 : 1
Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN1 : Capture Function Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated
#1 : 1
Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN2 : Capture Function Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated
#1 : 1
Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN3 : Capture Function Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated
#1 : 1
Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN4 : Capture Function Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated
#1 : 1
Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPEN5 : Capture Function Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture function Disabled. EPWM_RCAPDATn/EPWM_FCAPDATn register will not be updated
#1 : 1
Capture function Enabled. Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch)
End of enumeration elements list.
CAPINV0 : Capture Inverter Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV1 : Capture Inverter Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV2 : Capture Inverter Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV3 : Capture Inverter Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV4 : Capture Inverter Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
CAPINV5 : Capture Inverter Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture source inverter Disabled
#1 : 1
Capture source inverter Enabled. Reverse the input signal from GPIO
End of enumeration elements list.
RCRLDEN0 : Rising Capture Reload Enable Bits
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN1 : Rising Capture Reload Enable Bits
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN2 : Rising Capture Reload Enable Bits
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN3 : Rising Capture Reload Enable Bits
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN4 : Rising Capture Reload Enable Bits
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
RCRLDEN5 : Rising Capture Reload Enable Bits
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising capture reload counter Disabled
#1 : 1
Rising capture reload counter Enabled
End of enumeration elements list.
FCRLDEN0 : Falling Capture Reload Enable Bits
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN1 : Falling Capture Reload Enable Bits
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN2 : Falling Capture Reload Enable Bits
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN3 : Falling Capture Reload Enable Bits
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN4 : Falling Capture Reload Enable Bits
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
FCRLDEN5 : Falling Capture Reload Enable Bits
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling capture reload counter Disabled
#1 : 1
Falling capture reload counter Enabled
End of enumeration elements list.
EPWM Capture Status Register
address_offset : 0x208 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRLIFOV0 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]).
bits : 0 - 0 (1 bit)
access : read-only
CRLIFOV1 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]).
bits : 1 - 1 (1 bit)
access : read-only
CRLIFOV2 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]).
bits : 2 - 2 (1 bit)
access : read-only
CRLIFOV3 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]).
bits : 3 - 3 (1 bit)
access : read-only
CRLIFOV4 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]).
bits : 4 - 4 (1 bit)
access : read-only
CRLIFOV5 : Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIFn(EPWM_CAPIF[n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIFn(EPWM_CAPIF[n]).
bits : 5 - 5 (1 bit)
access : read-only
CFLIFOV0 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]).
bits : 8 - 8 (1 bit)
access : read-only
CFLIFOV1 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]).
bits : 9 - 9 (1 bit)
access : read-only
CFLIFOV2 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]).
bits : 10 - 10 (1 bit)
access : read-only
CFLIFOV3 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]).
bits : 11 - 11 (1 bit)
access : read-only
CFLIFOV4 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]).
bits : 12 - 12 (1 bit)
access : read-only
CFLIFOV5 : Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIFn(EPWM_CAPIF[8+n]) is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIFn(EPWM_CAPIF[8+n]).
bits : 13 - 13 (1 bit)
access : read-only
EPWM Rising Capture Data Register 0
address_offset : 0x20C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RCAPDAT : EPWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened, the EPWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
EPWM Falling Capture Data Register 0
address_offset : 0x210 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FCAPDAT : EPWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened, the EPWM counter value will be saved in this register.
bits : 0 - 15 (16 bit)
access : read-only
EPWM Rising Capture Data Register 1
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Falling Capture Data Register 1
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Rising Capture Data Register 2
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Falling Capture Data Register 2
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Rising Capture Data Register 3
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Falling Capture Data Register 3
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Rising Capture Data Register 4
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Falling Capture Data Register 4
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Rising Capture Data Register 5
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Falling Capture Data Register 5
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM PDMA Control Register
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0_1 : Channel 0/1 PDMA Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 0/1 PDMA function Disabled
#1 : 1
Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory
End of enumeration elements list.
CAPMOD0_1 : Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
EPWM_RCAPDAT0/1
#10 : 2
EPWM_FCAPDAT0/1
#11 : 3
Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1
End of enumeration elements list.
CAPORD0_1 : Capture Channel 0/1 Rising/Falling Order
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_FCAPDAT0/1 is the first captured data to memory
#1 : 1
EPWM_RCAPDAT0/1 is the first captured data to memory
End of enumeration elements list.
CHSEL0_1 : Select Channel 0/1 to Do PDMA Transfer
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel0
#1 : 1
Channel1
End of enumeration elements list.
CHEN2_3 : Channel 2/3 PDMA Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 2/3 PDMA function Disabled
#1 : 1
Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory
End of enumeration elements list.
CAPMOD2_3 : Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
EPWM_RCAPDAT2/3
#10 : 2
EPWM_FCAPDAT2/3
#11 : 3
Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3
End of enumeration elements list.
CAPORD2_3 : Capture Channel 2/3 Rising/Falling Order
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_FCAPDAT2/3 is the first captured data to memory
#1 : 1
EPWM_RCAPDAT2/3 is the first captured data to memory
End of enumeration elements list.
CHSEL2_3 : Select Channel 2/3 to Do PDMA Transfer
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel2
#1 : 1
Channel3
End of enumeration elements list.
CHEN4_5 : Channel 4/5 PDMA Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel 4/5 PDMA function Disabled
#1 : 1
Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory
End of enumeration elements list.
CAPMOD4_5 : Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer
bits : 17 - 18 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved.
#01 : 1
EPWM_RCAPDAT4/5
#10 : 2
EPWM_FCAPDAT4/5
#11 : 3
Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5
End of enumeration elements list.
CAPORD4_5 : Capture Channel 4/5 Rising/Falling Order
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_FCAPDAT4/5 is the first captured data to memory
#1 : 1
EPWM_RCAPDAT4/5 is the first captured data to memory
End of enumeration elements list.
CHSEL4_5 : Select Channel 4/5 to Do PDMA Transfer
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Channel4
#1 : 1
Channel5
End of enumeration elements list.
EPWM Clear Counter Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTCLR0 : Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit EPWM counter to 0000H
End of enumeration elements list.
CNTCLR1 : Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit EPWM counter to 0000H
End of enumeration elements list.
CNTCLR2 : Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit EPWM counter to 0000H
End of enumeration elements list.
CNTCLR3 : Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit EPWM counter to 0000H
End of enumeration elements list.
CNTCLR4 : Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit EPWM counter to 0000H
End of enumeration elements list.
CNTCLR5 : Clear EPWM Counter Control Bit\nIt is automatically cleared by hardware. Each bit n controls the corresponding EPWM channel n.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Clear 16-bit EPWM counter to 0000H
End of enumeration elements list.
EPWM Capture Channel 01 PDMA Register
address_offset : 0x240 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPBUF : EPWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer EPWM capture rising or falling data to memory by PDMA.
bits : 0 - 15 (16 bit)
access : read-only
EPWM Capture Channel 23 PDMA Register
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Capture Channel 45 PDMA Register
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Capture Interrupt Enable Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPRIEN0 : EPWM Capture Rising Latch Interrupt Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN1 : EPWM Capture Rising Latch Interrupt Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN2 : EPWM Capture Rising Latch Interrupt Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN3 : EPWM Capture Rising Latch Interrupt Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN4 : EPWM Capture Rising Latch Interrupt Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPRIEN5 : EPWM Capture Rising Latch Interrupt Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture rising edge latch interrupt Disabled
#1 : 1
Capture rising edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN0 : EPWM Capture Falling Latch Interrupt Enable Bits
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN1 : EPWM Capture Falling Latch Interrupt Enable Bits
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN2 : EPWM Capture Falling Latch Interrupt Enable Bits
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN3 : EPWM Capture Falling Latch Interrupt Enable Bits
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN4 : EPWM Capture Falling Latch Interrupt Enable Bits
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
CAPFIEN5 : EPWM Capture Falling Latch Interrupt Enable Bits
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture falling edge latch interrupt Disabled
#1 : 1
Capture falling edge latch interrupt Enabled
End of enumeration elements list.
EPWM Capture Interrupt Flag Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRLIF0 : EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF1 : EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF2 : EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF3 : EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF4 : EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CRLIF5 : EPWM Capture Rising Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CRLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture rising latch condition happened
#1 : 1
Capture rising latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF0 : EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF1 : EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF2 : EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF3 : EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF4 : EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
CFLIF5 : EPWM Capture Falling Latch Interrupt Flag\nNote1: When Capture with PDMA operating, EPWM_CAPIF corresponding channel CFLIFn will be cleared by hardware after PDMA transfer data.\nNote2: This bit is cleared by writing 1 to it.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No capture falling latch condition happened
#1 : 1
Capture falling latch condition happened, this flag will be set to high
End of enumeration elements list.
EPWM Load Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD0 : Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation:
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD1 : Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation:
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD2 : Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation:
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD3 : Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation:
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD4 : Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation:
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
LOAD5 : Re-load EPWM Comparator Register (EPWM_CMPDATn) Control Bit\nThis bit is software write, hardware clear when current EPWM period end.\nWrite Operation:
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNo load window is set
#1 : 1
Set load window of window loading mode.\nLoad window is set
End of enumeration elements list.
EPWM Period Register 0
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : EPWM Period Register\nUp-Count mode: \nIn this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0.
bits : 0 - 15 (16 bit)
access : read-write
EPWM PERIOD0 Buffer
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PBUF : EPWM Period Register Buffer (Read Only)\nUsed as PERIOD active register.
bits : 0 - 15 (16 bit)
access : read-only
EPWM PERIOD1 Buffer
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM PERIOD2 Buffer
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM PERIOD3 Buffer
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM PERIOD4 Buffer
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM PERIOD5 Buffer
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CMPDAT0 Buffer
address_offset : 0x31C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CMPBUF : EPWM Comparator Register Buffer (Read Only)\nUsed as CMP active register.
bits : 0 - 15 (16 bit)
access : read-only
EPWM CMPDAT1 Buffer
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CMPDAT2 Buffer
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CMPDAT3 Buffer
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CMPDAT4 Buffer
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CMPDAT5 Buffer
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CLKPSC0_1 Buffer
address_offset : 0x334 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CPSCBUF : EPWM Counter Clock Prescale Buffer\nUsed as EPWM counter clock pre-scare active register.
bits : 0 - 11 (12 bit)
access : read-only
EPWM CLKPSC2_3 Buffer
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM CLKPSC4_5 Buffer
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Period Register 1
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM FTCMPDAT0_1 Buffer
address_offset : 0x340 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FTCMPBUF : EPWM FTCMPDAT Buffer (Read Only)\nUsed as FTCMP active buffer.
bits : 0 - 15 (16 bit)
access : read-only
EPWM FTCMPDAT2_3 Buffer
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM FTCMPDAT4_5 Buffer
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM FTCMPDAT Indicator Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTCMU0 : EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
FTCMU2 : EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
FTCMU4 : EPWM FTCMPDAT Up Indicator\nIndicator is set by hardware when EPWM counter up count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write
FTCMD0 : EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
FTCMD2 : EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
FTCMD4 : EPWM FTCMPDAT Down Indicator\nIndicator is set by hardware when EPWM counter down count and reaches EPWM_FTCMPDATn, software can clear this bit by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
EPWM Period Register 2
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Period Register 3
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Control Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTTYPE0 : EPWM Counter Behavior Type
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE1 : EPWM Counter Behavior Type
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE2 : EPWM Counter Behavior Type
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE3 : EPWM Counter Behavior Type
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE4 : EPWM Counter Behavior Type
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTTYPE5 : EPWM Counter Behavior Type
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Up counter type (supported in capture mode)
#01 : 1
Down count type (supported in capture mode)
#10 : 2
Up-down counter type
#11 : 3
Reserved.
End of enumeration elements list.
CNTMODE0 : EPWM Counter Mode
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE1 : EPWM Counter Mode
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE2 : EPWM Counter Mode
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE3 : EPWM Counter Mode
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE4 : EPWM Counter Mode
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
CNTMODE5 : EPWM Counter Mode
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-reload mode
#1 : 1
One-shot mode
End of enumeration elements list.
OUTMODE0 : EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM independent mode
#1 : 1
EPWM complementary mode
End of enumeration elements list.
OUTMODE2 : EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM independent mode
#1 : 1
EPWM complementary mode
End of enumeration elements list.
OUTMODE4 : EPWM Output Mode\nEach bit n controls the output mode of corresponding EPWM channel n.\nNote: When operating in group function, these bits must all set to the same mode.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM independent mode
#1 : 1
EPWM complementary mode
End of enumeration elements list.
EPWM Period Register 4
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Period Register 5
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP : EPWM Comparator Register\nCMP is used to compare with CNT (EPWM_CNTn[15:0]) bits to generate EPWM waveform, interrupt and trigger EADC/DAC.\nIn complementary mode, EPWM_CMPDAT0, EPWM_CMPDAT 2, EPWM_CMPDAT4 denote as first compared point, and EPWM_CMPDAT1, EPWM_CMPDAT3, EPWM_CMPDAT5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5.
bits : 0 - 15 (16 bit)
access : read-write
EPWM Comparator Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 2
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 3
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 4
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Comparator Register 5
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Dead-time Control Register 0/1
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTCNT : Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 11 (12 bit)
access : read-write
DTEN : Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect)\nDead-time insertion is only active when this pair of complementary EPWM is enabled. If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time insertion Disabled on the pin pair
#1 : 1
Dead-time insertion Enabled on the pin pair
End of enumeration elements list.
DTCKSEL : Dead-time Clock Select (Write Protect)\nNote: This bit is write protected. Refer to REGWRPROT register.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Dead-time clock source from EPWM_CLK
#1 : 1
Dead-time clock source from prescaler output
End of enumeration elements list.
EPWM Dead-time Control Register 2/3
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Dead-time Control Register 4/5
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Synchronization Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHSEN0 : SYNC Phase Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM counter disable to load PHS value
#1 : 1
EPWM counter enable to load PHS value
End of enumeration elements list.
PHSEN2 : SYNC Phase Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM counter disable to load PHS value
#1 : 1
EPWM counter enable to load PHS value
End of enumeration elements list.
PHSEN4 : SYNC Phase Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM counter disable to load PHS value
#1 : 1
EPWM counter enable to load PHS value
End of enumeration elements list.
SINSRC0 : EPWM0_SYNC_IN Source Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT will not be generated
End of enumeration elements list.
SINSRC2 : EPWM0_SYNC_IN Source Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT will not be generated
End of enumeration elements list.
SINSRC4 : EPWM0_SYNC_IN Source Selection
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
Synchronize source from SYNC_IN or SWSYNC
#01 : 1
Counter equal to 0
#10 : 2
Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5
#11 : 3
SYNC_OUT will not be generated
End of enumeration elements list.
SNFLTEN : EPWM0_SYNC_IN Noise Filter Enable Bits
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of input pin EPWM0_SYNC_IN Disabled
#1 : 1
Noise filter of input pin EPWM0_SYNC_IN Enabled
End of enumeration elements list.
SFLTCSEL : SYNC Edge Detector Filter Clock Selection
bits : 17 - 19 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
SFLTCNT : SYNC Edge Detector Filter Count\nThe register bits control the counter number of edge detector.
bits : 20 - 22 (3 bit)
access : read-write
SINPINV : SYNC Input Pin Inverse
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The state of pin SYNC is passed to the negative edge detector
#1 : 1
The inversed state of pin SYNC is passed to the negative edge detector
End of enumeration elements list.
PHSDIR0 : EPWM Phase Direction Control
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control EPWM counter count decrement after synchronizing
#1 : 1
Control EPWM counter count increment after synchronizing
End of enumeration elements list.
PHSDIR2 : EPWM Phase Direction Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control EPWM counter count decrement after synchronizing
#1 : 1
Control EPWM counter count increment after synchronizing
End of enumeration elements list.
PHSDIR4 : EPWM Phase Direction Control
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Control EPWM counter count decrement after synchronizing
#1 : 1
Control EPWM counter count increment after synchronizing
End of enumeration elements list.
EPWM Counter Phase Register 0/1
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHS : EPWM Synchronous Start Phase Bits\nPHS determines the EPWM synchronous start phase value. These bits only use in synchronous function.
bits : 0 - 15 (16 bit)
access : read-write
EPWM Counter Phase Register 2/3
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Phase Register 4/5
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Register 0
address_offset : 0x90 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : EPWM Data Register (Read Only)\nUser can monitor CNT to know the current value in 16-bit period counter.
bits : 0 - 15 (16 bit)
access : read-only
DIRF : EPWM Direction Indicator Flag (Read Only)
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Counter is counting down
#1 : 1
Counter is counting up
End of enumeration elements list.
EPWM Counter Register 1
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Register 2
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Register 3
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Register 4
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Counter Register 5
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Generation Register 0
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZPCTL0 : EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM zero point output Low
#10 : 2
EPWM zero point output High
#11 : 3
EPWM zero point output Toggle
End of enumeration elements list.
ZPCTL1 : EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM zero point output Low
#10 : 2
EPWM zero point output High
#11 : 3
EPWM zero point output Toggle
End of enumeration elements list.
ZPCTL2 : EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM zero point output Low
#10 : 2
EPWM zero point output High
#11 : 3
EPWM zero point output Toggle
End of enumeration elements list.
ZPCTL3 : EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM zero point output Low
#10 : 2
EPWM zero point output High
#11 : 3
EPWM zero point output Toggle
End of enumeration elements list.
ZPCTL4 : EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM zero point output Low
#10 : 2
EPWM zero point output High
#11 : 3
EPWM zero point output Toggle
End of enumeration elements list.
ZPCTL5 : EPWM Zero Point Control\nEPWM can control output level when EPWM counter counts to 0.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM zero point output Low
#10 : 2
EPWM zero point output High
#11 : 3
EPWM zero point output Toggle
End of enumeration elements list.
PRDPCTL0 : EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM period (center) point output Low
#10 : 2
EPWM period (center) point output High
#11 : 3
EPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL1 : EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM period (center) point output Low
#10 : 2
EPWM period (center) point output High
#11 : 3
EPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL2 : EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM period (center) point output Low
#10 : 2
EPWM period (center) point output High
#11 : 3
EPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL3 : EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM period (center) point output Low
#10 : 2
EPWM period (center) point output High
#11 : 3
EPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL4 : EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM period (center) point output Low
#10 : 2
EPWM period (center) point output High
#11 : 3
EPWM period (center) point output Toggle
End of enumeration elements list.
PRDPCTL5 : EPWM Period (Center) Point Control\nEPWM can control output level when EPWM counter counts to (PERIODn+1).\nNote: This bit is center point control when EPWM counter operating in up-down counter type.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM period (center) point output Low
#10 : 2
EPWM period (center) point output High
#11 : 3
EPWM period (center) point output Toggle
End of enumeration elements list.
EPWM Generation Register 1
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPUCTL0 : EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare up point output Low
#10 : 2
EPWM compare up point output High
#11 : 3
EPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL1 : EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare up point output Low
#10 : 2
EPWM compare up point output High
#11 : 3
EPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL2 : EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare up point output Low
#10 : 2
EPWM compare up point output High
#11 : 3
EPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL3 : EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare up point output Low
#10 : 2
EPWM compare up point output High
#11 : 3
EPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL4 : EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare up point output Low
#10 : 2
EPWM compare up point output High
#11 : 3
EPWM compare up point output Toggle
End of enumeration elements list.
CMPUCTL5 : EPWM Compare Up Point Control\nEPWM can control output level when EPWM counter counts up to CMP.\nNote: In complementary mode, CMPUCTL1, 3, 5 is used as another CMPUCTL for channel 0, 2, 4.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare up point output Low
#10 : 2
EPWM compare up point output High
#11 : 3
EPWM compare up point output Toggle
End of enumeration elements list.
CMPDCTL0 : EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare down point output Low
#10 : 2
EPWM compare down point output High
#11 : 3
EPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL1 : EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare down point output Low
#10 : 2
EPWM compare down point output High
#11 : 3
EPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL2 : EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare down point output Low
#10 : 2
EPWM compare down point output High
#11 : 3
EPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL3 : EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare down point output Low
#10 : 2
EPWM compare down point output High
#11 : 3
EPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL4 : EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare down point output Low
#10 : 2
EPWM compare down point output High
#11 : 3
EPWM compare down point output Toggle
End of enumeration elements list.
CMPDCTL5 : EPWM Compare Down Point Control\nEPWM can control output level when EPWM counter counts down to CMP.\nNote: In complementary mode, CMPDCTL1, 3, 5 is used as another CMPDCTL for channel 0, 2, 4.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
Do nothing
#01 : 1
EPWM compare down point output Low
#10 : 2
EPWM compare down point output High
#11 : 3
EPWM compare down point output Toggle
End of enumeration elements list.
EPWM Mask Enable Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKEN0 : EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM output signal is non-masked
#1 : 1
EPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN1 : EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM output signal is non-masked
#1 : 1
EPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN2 : EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM output signal is non-masked
#1 : 1
EPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN3 : EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM output signal is non-masked
#1 : 1
EPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN4 : EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM output signal is non-masked
#1 : 1
EPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
MSKEN5 : EPWM Mask Enable Bits\nThe EPWM output signal will be masked when this bit is enabled. The corresponding EPWM channel n will output MSKDATn (EPWM_MSK[5:0]) data.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM output signal is non-masked
#1 : 1
EPWM output signal is masked and output MSKDATn data
End of enumeration elements list.
EPWM Mask Data Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSKDAT0 : EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to EPWM channel n
#1 : 1
Output logic high to EPWM channel n
End of enumeration elements list.
MSKDAT1 : EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to EPWM channel n
#1 : 1
Output logic high to EPWM channel n
End of enumeration elements list.
MSKDAT2 : EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to EPWM channel n
#1 : 1
Output logic high to EPWM channel n
End of enumeration elements list.
MSKDAT3 : EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to EPWM channel n
#1 : 1
Output logic high to EPWM channel n
End of enumeration elements list.
MSKDAT4 : EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to EPWM channel n
#1 : 1
Output logic high to EPWM channel n
End of enumeration elements list.
MSKDAT5 : EPWM Mask Data Bit\nThis data bit control the state of EPWMn output pin, if corresponding mask function is enabled.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Output logic low to EPWM channel n
#1 : 1
Output logic high to EPWM channel n
End of enumeration elements list.
EPWM Software Control Synchronization Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWSYNC0 : Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit.
bits : 0 - 0 (1 bit)
access : read-write
SWSYNC2 : Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit.
bits : 1 - 1 (1 bit)
access : read-write
SWSYNC4 : Software SYNC Function\nWhen SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source comes from SYNC_IN or this bit.
bits : 2 - 2 (1 bit)
access : read-write
EPWM Brake Noise Filter Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRK0NFEN : EPWM Brake 0 Noise Filter Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of EPWM Brake 0 Disabled
#1 : 1
Noise filter of EPWM Brake 0 Enabled
End of enumeration elements list.
BRK0NFSEL : Brake 0 Edge Detector Filter Clock Selection
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK0FCNT : Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK0FCNT.
bits : 4 - 6 (3 bit)
access : read-write
BRK0PINV : Brake 0 Pin Inverse
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from low to high in edge-detect, or pin status is high in level-detect
#1 : 1
brake pin event will be detected if EPWMx_BRAKE0 pin status transfer from high to low in edge-detect, or pin status is low in level-detect
End of enumeration elements list.
BRK1NFEN : EPWM Brake 1 Noise Filter Enable Bit
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Noise filter of EPWM Brake 1 Disabled
#1 : 1
Noise filter of EPWM Brake 1 Enabled
End of enumeration elements list.
BRK1NFSEL : Brake 1 Edge Detector Filter Clock Selection
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
#000 : 0
Filter clock = HCLK
#001 : 1
Filter clock = HCLK/2
#010 : 2
Filter clock = HCLK/4
#011 : 3
Filter clock = HCLK/8
#100 : 4
Filter clock = HCLK/16
#101 : 5
Filter clock = HCLK/32
#110 : 6
Filter clock = HCLK/64
#111 : 7
Filter clock = HCLK/128
End of enumeration elements list.
BRK1FCNT : Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
bits : 12 - 14 (3 bit)
access : read-write
BRK1PINV : Brake 1 Pin Inverse
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from low to high in edge-detect, or pin status is high in level-detect
#1 : 1
brake pin event will be detected if EPWMx_BRAKE1 pin status transfer from high to low in edge-detect, or pin status is low in level-detect
End of enumeration elements list.
BK0SRC : Brake 0 Pin Source Select\nFor EPWM0 setting:
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 0 pin source come from EPWM0_BRAKE0.\nBrake 0 pin source come from EPWM1_BRAKE0
#1 : 1
Brake 0 pin source come from EPWM1_BRAKE0.\nBrake 0 pin source come from EPWM0_BRAKE0
End of enumeration elements list.
BK1SRC : Brake 1 Pin Source Select\nFor EPWM0 setting:
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake 1 pin source come from EPWM0_BRAKE1.\nBrake 1 pin source come from EPWM1_BRAKE1
#1 : 1
Brake 1 pin source come from EPWM1_BRAKE1.\nBrake 1 pin source come from EPWM0_BRAKE1
End of enumeration elements list.
EPWM System Fail Brake Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSSBRKEN : Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by CSS detection Disabled
#1 : 1
Brake Function triggered by CSS detection Enabled
End of enumeration elements list.
BODBRKEN : Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by BOD Disabled
#1 : 1
Brake Function triggered by BOD Enabled
End of enumeration elements list.
RAMBRKEN : SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by SRAM parity error detection Disabled
#1 : 1
Brake Function triggered by SRAM parity error detection Enabled
End of enumeration elements list.
CORBRKEN : Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brake Function triggered by Core lockup detection Disabled
#1 : 1
Brake Function triggered by Core lockup detection Enabled
End of enumeration elements list.
EPWM Brake Detect Control Register 0/1
address_offset : 0xC8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPO0EBEN : Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0_O as edge-detect brake source Disabled
#1 : 1
ACMP0_O as edge-detect brake source Enabled
End of enumeration elements list.
CPO1EBEN : Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_O as edge-detect brake source Disabled
#1 : 1
ACMP1_O as edge-detect brake source Enabled
End of enumeration elements list.
BRKP0EEN : Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_BRAKE0 pin as edge-detect brake source Disabled
#1 : 1
EPWMx_BRAKE0 pin as edge-detect brake source Enabled
End of enumeration elements list.
BRKP1EEN : Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_BRAKE1 pin as edge-detect brake source Disabled
#1 : 1
EPWMx_BRAKE1 pin as edge-detect brake source Enabled
End of enumeration elements list.
SYSEBEN : Enable System Fail As Edge-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as edge-detect brake source Disabled
#1 : 1
System Fail condition as edge-detect brake source Enabled
End of enumeration elements list.
CPO0LBEN : Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP0_O as level-detect brake source Disabled
#1 : 1
ACMP0_O as level-detect brake source Enabled
End of enumeration elements list.
CPO1LBEN : Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ACMP1_O as level-detect brake source Disabled
#1 : 1
ACMP1_O as level-detect brake source Enabled
End of enumeration elements list.
BRKP0LEN : Enable BKP0 Pin As Level-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_BRAKE0 pin as level-detect brake source Disabled
#1 : 1
EPWMx_BRAKE0 pin as level-detect brake source Enabled
End of enumeration elements list.
BRKP1LEN : Enable BKP1 Pin As Level-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_BRAKE1 pin as level-detect brake source Disabled
#1 : 1
EPWMx_BRAKE1 pin as level-detect brake source Enabled
End of enumeration elements list.
SYSLBEN : Enable System Fail As Level-detect Brake Source (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Fail condition as level-detect brake source Disabled
#1 : 1
System Fail condition as level-detect brake source Enabled
End of enumeration elements list.
BRKAEVEN : EPWM Brake Action Select for Even Channel (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
EPWMx brake event will not affect even channels output
#01 : 1
EPWM even channel output tri-state when EPWMx brake event happened
#10 : 2
EPWM even channel output low level when EPWMx brake event happened
#11 : 3
EPWM even channel output high level when EPWMx brake event happened
End of enumeration elements list.
BRKAODD : EPWM Brake Action Select for Odd Channel (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
EPWMx brake event will not affect odd channels output
#01 : 1
EPWM odd channel output tri-state when EPWMx brake event happened
#10 : 2
EPWM odd channel output low level when EPWMx brake event happened
#11 : 3
EPWM odd channel output high level when EPWMx brake event happened
End of enumeration elements list.
EADC0EBEN : Enable EADC0 Result Monitor (EADC0RM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC0RM as edge-detect brake source Disabled
#1 : 1
EADC0RM as edge-detect brake source Enabled
End of enumeration elements list.
EADC1EBEN : Enable EADC1 Result Monitor (EADC1RM) As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC1RM as edge-detect brake source Disabled
#1 : 1
EADC1RM as edge-detect brake source Enabled
End of enumeration elements list.
EADC0LBEN : Enable EADC0 Result Monitor (EADC0RM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC0RM as level-detect brake source Disabled
#1 : 1
EADC0RM as level-detect brake source Enabled
End of enumeration elements list.
EADC1LBEN : Enable EADC1 Result Monitor (EADC1RM) As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC1RM as level-detect brake source Disabled
#1 : 1
EADC1RM as level-detect brake source Enabled
End of enumeration elements list.
EPWM Brake Detect Control Register 2/3
address_offset : 0xCC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Brake Detect Control Register 4/5
address_offset : 0xD0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPWM Pin Polar Inverse Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PINV0 : EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn output pin polar inverse Disabled
#1 : 1
EPWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV1 : EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn output pin polar inverse Disabled
#1 : 1
EPWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV2 : EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn output pin polar inverse Disabled
#1 : 1
EPWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV3 : EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn output pin polar inverse Disabled
#1 : 1
EPWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV4 : EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn output pin polar inverse Disabled
#1 : 1
EPWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
PINV5 : EPWM PIN Polar Inverse Control\nThe register controls polarity state of EPWMx_CHn output pin.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn output pin polar inverse Disabled
#1 : 1
EPWMx_CHn output pin polar inverse Enabled
End of enumeration elements list.
EPWM Output Enable Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POEN0 : EPWM Pin Output Enable Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn pin at tri-state
#1 : 1
EPWMx_CHn pin in output mode
End of enumeration elements list.
POEN1 : EPWM Pin Output Enable Bits
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn pin at tri-state
#1 : 1
EPWMx_CHn pin in output mode
End of enumeration elements list.
POEN2 : EPWM Pin Output Enable Bits
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn pin at tri-state
#1 : 1
EPWMx_CHn pin in output mode
End of enumeration elements list.
POEN3 : EPWM Pin Output Enable Bits
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn pin at tri-state
#1 : 1
EPWMx_CHn pin in output mode
End of enumeration elements list.
POEN4 : EPWM Pin Output Enable Bits
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn pin at tri-state
#1 : 1
EPWMx_CHn pin in output mode
End of enumeration elements list.
POEN5 : EPWM Pin Output Enable Bits
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWMx_CHn pin at tri-state
#1 : 1
EPWMx_CHn pin in output mode
End of enumeration elements list.
EPWM Software Brake Control Register
address_offset : 0xDC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
BRKETRG0 : EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : write-only
BRKETRG2 : EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : write-only
BRKETRG4 : EPWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : write-only
BRKLTRG0 : EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : write-only
BRKLTRG2 : EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : write-only
BRKLTRG4 : EPWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake, and set BRKLIFn to 1 in EPWM_INTSTS1 register. \nNote: This bit is write protected. Refer to SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : write-only
EPWM Interrupt Enable Register 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIEN0 : EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN1 : EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN2 : EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN3 : EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN4 : EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
ZIEN5 : EPWM Zero Point Interrupt Enable Bits\nNote: Odd channels will read always 0 at complementary mode.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Zero point interrupt Disabled
#1 : 1
Zero point interrupt Enabled
End of enumeration elements list.
PIEN0 : EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN1 : EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN2 : EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN3 : EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN4 : EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
PIEN5 : EPWM Period Point Interrupt Enable Bits\nNote1: When up-down counter type period point means center point.\nNote2: Odd channels will read always 0 at complementary mode.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Period point interrupt Disabled
#1 : 1
Period point interrupt Enabled
End of enumeration elements list.
CMPUIEN0 : EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN1 : EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN2 : EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN3 : EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN4 : EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPUIEN5 : EPWM Compare Up Count Interrupt Enable Bits\nNote: In complementary mode, CMPUIEN1, 3, 5 is used as another CMPUIEN for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare up count interrupt Disabled
#1 : 1
Compare up count interrupt Enabled
End of enumeration elements list.
CMPDIEN0 : EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN1 : EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN2 : EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN3 : EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN4 : EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
CMPDIEN5 : EPWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode, CMPDIEN1, 3, 5 is used as another CMPDIEN for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare down count interrupt Disabled
#1 : 1
Compare down count interrupt Enabled
End of enumeration elements list.
EPWM Interrupt Enable Register 1
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIEN0_1 : EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Edge-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKEIEN2_3 : EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Edge-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKEIEN4_5 : EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Edge-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
BRKLIEN0_1 : EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel0/1 Disabled
#1 : 1
Level-detect Brake interrupt for channel0/1 Enabled
End of enumeration elements list.
BRKLIEN2_3 : EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel2/3 Disabled
#1 : 1
Level-detect Brake interrupt for channel2/3 Enabled
End of enumeration elements list.
BRKLIEN4_5 : EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Level-detect Brake interrupt for channel4/5 Disabled
#1 : 1
Level-detect Brake interrupt for channel4/5 Enabled
End of enumeration elements list.
EPWM Interrupt Flag Register 0
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZIF0 : EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1
bits : 0 - 0 (1 bit)
access : read-write
ZIF1 : EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1
bits : 1 - 1 (1 bit)
access : read-write
ZIF2 : EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1
bits : 2 - 2 (1 bit)
access : read-write
ZIF3 : EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1
bits : 3 - 3 (1 bit)
access : read-write
ZIF4 : EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1
bits : 4 - 4 (1 bit)
access : read-write
ZIF5 : EPWM Zero Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches 0. \nNote: This bit can be cleared to 0 by software writing 1
bits : 5 - 5 (1 bit)
access : read-write
PIF0 : EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1.
bits : 8 - 8 (1 bit)
access : read-write
PIF1 : EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1.
bits : 9 - 9 (1 bit)
access : read-write
PIF2 : EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1.
bits : 10 - 10 (1 bit)
access : read-write
PIF3 : EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1.
bits : 11 - 11 (1 bit)
access : read-write
PIF4 : EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1.
bits : 12 - 12 (1 bit)
access : read-write
PIF5 : EPWM Period Point Interrupt Flag\nThis bit is set by hardware when EPWM counter reaches EPWM_PERIODn. \nNote: This bit can be cleared to 0 by software writing 1.
bits : 13 - 13 (1 bit)
access : read-write
CMPUIF0 : EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
CMPUIF1 : EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
CMPUIF2 : EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
CMPUIF3 : EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
CMPUIF4 : EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
CMPUIF5 : EPWM Compare Up Count Interrupt Flag\nFlag is set by hardware when EPWM counter up count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPUIF1, 3, 5 is used as another CMPUIF for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
CMPDIF0 : EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
CMPDIF1 : EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
CMPDIF2 : EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
CMPDIF3 : EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
CMPDIF4 : EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
CMPDIF5 : EPWM Compare Down Count Interrupt Flag\nFlag is set by hardware when EPWM counter down count and reaches EPWM_CMPDATn, software can clear this bit by writing 1 to it.\nNote: In complementary mode, CMPDIF1, 3, 5 is used as another CMPDIF for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
EPWM Interrupt Flag Register 1
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKEIF0 : EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n edge-detect brake event do not happened
#1 : 1
When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF1 : EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n edge-detect brake event do not happened
#1 : 1
When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF2 : EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n edge-detect brake event do not happened
#1 : 1
When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF3 : EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n edge-detect brake event do not happened
#1 : 1
When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF4 : EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n edge-detect brake event do not happened
#1 : 1
When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKEIF5 : EPWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n edge-detect brake event do not happened
#1 : 1
When EPWM channel n edge-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF0 : EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n level-detect brake event do not happened
#1 : 1
When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF1 : EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n level-detect brake event do not happened
#1 : 1
When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF2 : EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n level-detect brake event do not happened
#1 : 1
When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF3 : EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n level-detect brake event do not happened
#1 : 1
When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF4 : EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n level-detect brake event do not happened
#1 : 1
When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKLIF5 : EPWM Channel N Level-detect Brake Interrupt Flag (Write Protect)
Note: This bit is write protected. Refer toSYS_REGLCTL register.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM channel n level-detect brake event do not happened
#1 : 1
When EPWM channel n level-detect brake event happened, this bit is set to 1, writing 1 to clear
End of enumeration elements list.
BRKESTS0 : EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n edge-detect brake state is released
#1 : 1
When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKESTS1 : EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n edge-detect brake state is released
#1 : 1
When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKESTS2 : EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n edge-detect brake state is released
#1 : 1
When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKESTS3 : EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n edge-detect brake state is released
#1 : 1
When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKESTS4 : EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n edge-detect brake state is released
#1 : 1
When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKESTS5 : EPWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When edge-detect brake interrupt flag is cleared, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n edge-detect brake state is released
#1 : 1
When EPWM channel n edge-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKLSTS0 : EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n level-detect brake state is released
#1 : 1
When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKLSTS1 : EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n level-detect brake state is released
#1 : 1
When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKLSTS2 : EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n level-detect brake state is released
#1 : 1
When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKLSTS3 : EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n level-detect brake state is released
#1 : 1
When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKLSTS4 : EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n level-detect brake state is released
#1 : 1
When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
BRKLSTS5 : EPWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware. When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished. The EPWM waveform will start output from next full EPWM period.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
#0 : 0
EPWM channel n level-detect brake state is released
#1 : 1
When EPWM channel n level-detect brake detects a falling edge of any enabled brake source this flag will be set to indicate the EPWM channel n at brake state
End of enumeration elements list.
EPWM Trigger DAC Enable Register
address_offset : 0xF4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ZTE0 : EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
ZTE1 : EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
ZTE2 : EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
ZTE3 : EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
ZTE4 : EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
ZTE5 : EPWM Zero Point Trigger DAC Enable Bits\nEPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
PTE0 : EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
PTE1 : EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
PTE2 : EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
PTE3 : EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
PTE4 : EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
PTE5 : EPWM Period Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to (PERIODn+1) if this bit is set to1.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM period point trigger DAC function Disabled
#1 : 1
EPWM period point trigger DAC function Enabled
End of enumeration elements list.
CUTRGEN0 : EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Up point trigger DAC function Disabled
#1 : 1
EPWM Compare Up point trigger DAC function Enabled
End of enumeration elements list.
CUTRGEN1 : EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Up point trigger DAC function Disabled
#1 : 1
EPWM Compare Up point trigger DAC function Enabled
End of enumeration elements list.
CUTRGEN2 : EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Up point trigger DAC function Disabled
#1 : 1
EPWM Compare Up point trigger DAC function Enabled
End of enumeration elements list.
CUTRGEN3 : EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Up point trigger DAC function Disabled
#1 : 1
EPWM Compare Up point trigger DAC function Enabled
End of enumeration elements list.
CUTRGEN4 : EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Up point trigger DAC function Disabled
#1 : 1
EPWM Compare Up point trigger DAC function Enabled
End of enumeration elements list.
CUTRGEN5 : EPWM Compare Up Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter counts up to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in down counter type.\nNote2: In complementary mode, CUTRGEN1, 3, 5 is used as another CUTRGEN for channel 0, 2, 4.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Up point trigger DAC function Disabled
#1 : 1
EPWM Compare Up point trigger DAC function Enabled
End of enumeration elements list.
CDTRGEN0 : EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Down count point trigger DAC function Disabled
#1 : 1
EPWM Compare Down count point trigger DAC function Enabled
End of enumeration elements list.
CDTRGEN1 : EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Down count point trigger DAC function Disabled
#1 : 1
EPWM Compare Down count point trigger DAC function Enabled
End of enumeration elements list.
CDTRGEN2 : EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Down count point trigger DAC function Disabled
#1 : 1
EPWM Compare Down count point trigger DAC function Enabled
End of enumeration elements list.
CDTRGEN3 : EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Down count point trigger DAC function Disabled
#1 : 1
EPWM Compare Down count point trigger DAC function Enabled
End of enumeration elements list.
CDTRGEN4 : EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Down count point trigger DAC function Disabled
#1 : 1
EPWM Compare Down count point trigger DAC function Enabled
End of enumeration elements list.
CDTRGEN5 : EPWM Compare Down Count Point Trigger DAC Enable Bits\nEPWM can trigger DAC to start action when EPWM counter down count to CMP if this bit is set to1.\nNote1: This bit should keep at 0 when EPWM counter operating in up counter type.\nNote2: In complementary mode, CDTRGEN1, 3, 5 is used as another CDTRGEN for channel 0, 2, 4.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM Compare Down count point trigger DAC function Disabled
#1 : 1
EPWM Compare Down count point trigger DAC function Enabled
End of enumeration elements list.
EPWM Trigger EADC Source Select Register 0
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL0 : EPWM_CH0 Trigger EADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
EPWM_CH0 zero point
#0001 : 1
EPWM_CH0 period point
#0010 : 2
EPWM_CH0 zero or period point
#0011 : 3
EPWM_CH0 up-count compared point
#0100 : 4
EPWM_CH0 down-count compared point
#0101 : 5
EPWM_CH1 zero point
#0110 : 6
EPWM_CH1 period point
#0111 : 7
EPWM_CH1 zero or period point
#1000 : 8
EPWM_CH1 up-count compared point
#1001 : 9
EPWM_CH1 down-count compared point
#1010 : 10
EPWM_CH0 up-count free trigger compared point
#1011 : 11
EPWM_CH0 down-count free trigger compared point
#1100 : 12
EPWM_CH2 up-count free trigger compared point
#1101 : 13
EPWM_CH2 down-count free trigger compared point
#1110 : 14
EPWM_CH4 up-count free trigger compared point
#1111 : 15
EPWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN0 : EPWM_CH0 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH0 Trigger EADC function Disabled
#1 : 1
EPWM_CH0 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL1 : EPWM_CH1 Trigger EADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
EPWM_CH0 zero point
#0001 : 1
EPWM_CH0 period point
#0010 : 2
EPWM_CH0 zero or period point
#0011 : 3
EPWM_CH0 up-count compared point
#0100 : 4
EPWM_CH0 down-count compared point
#0101 : 5
EPWM_CH1 zero point
#0110 : 6
EPWM_CH1 period point
#0111 : 7
EPWM_CH1 zero or period point
#1000 : 8
EPWM_CH1 up-count compared point
#1001 : 9
EPWM_CH1 down-count compared point
#1010 : 10
EPWM_CH0 up-count free trigger compared point
#1011 : 11
EPWM_CH0 down-count free trigger compared point
#1100 : 12
EPWM_CH2 up-count free trigger compared point
#1101 : 13
EPWM_CH2 down-count free trigger compared point
#1110 : 14
EPWM_CH4 up-count free trigger compared point
#1111 : 15
EPWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN1 : EPWM_CH1 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH1 Trigger EADC function Disabled
#1 : 1
EPWM_CH1 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL2 : EPWM_CH2 Trigger EADC Source Select
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
EPWM_CH2 zero point
#0001 : 1
EPWM_CH2 period point
#0010 : 2
EPWM_CH2 zero or period point
#0011 : 3
EPWM_CH2 up-count compared point
#0100 : 4
EPWM_CH2 down-count compared point
#0101 : 5
EPWM_CH3 zero point
#0110 : 6
EPWM_CH3 period point
#0111 : 7
EPWM_CH3 zero or period point
#1000 : 8
EPWM_CH3 up-count compared point
#1001 : 9
EPWM_CH3 down-count compared point
#1010 : 10
EPWM_CH0 up-count free trigger compared point
#1011 : 11
EPWM_CH0 down-count free trigger compared point
#1100 : 12
EPWM_CH2 up-count free trigger compared point
#1101 : 13
EPWM_CH2 down-count free trigger compared point
#1110 : 14
EPWM_CH4 up-count free trigger compared point
#1111 : 15
EPWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN2 : EPWM_CH2 Trigger EADC Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH2 Trigger EADC function Disabled
#1 : 1
EPWM_CH2 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL3 : EPWM_CH3 Trigger EADC Source Select
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
EPWM_CH2 zero point
#0001 : 1
EPWM_CH2 period point
#0010 : 2
EPWM_CH2 zero or period point
#0011 : 3
EPWM_CH2 up-count compared point
#0100 : 4
EPWM_CH2 down-count compared point
#0101 : 5
EPWM_CH3 zero point
#0110 : 6
EPWM_CH3 period point
#0111 : 7
EPWM_CH3 zero or period point
#1000 : 8
EPWM_CH3 up-count compared point
#1001 : 9
EPWM_CH3 down-count compared point
#1010 : 10
EPWM_CH0 up-count free trigger compared point
#1011 : 11
EPWM_CH0 down-count free trigger compared point
#1100 : 12
EPWM_CH2 up-count free trigger compared point
#1101 : 13
EPWM_CH2 down-count free trigger compared point
#1110 : 14
EPWM_CH4 up-count free trigger compared point
#1111 : 15
EPWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN3 : EPWM_CH3 Trigger EADC Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH3 Trigger EADC function Disabled
#1 : 1
EPWM_CH3 Trigger EADC function Enabled
End of enumeration elements list.
EPWM Trigger EADC Source Select Register 1
address_offset : 0xFC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRGSEL4 : EPWM_CH4 Trigger EADC Source Select
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
EPWM_CH4 zero point
#0001 : 1
EPWM_CH4 period point
#0010 : 2
EPWM_CH4 zero or period point
#0011 : 3
EPWM_CH4 up-count compared point
#0100 : 4
EPWM_CH4 down-count compared point
#0101 : 5
EPWM_CH5 zero point
#0110 : 6
EPWM_CH5 period point
#0111 : 7
EPWM_CH5 zero or period point
#1000 : 8
EPWM_CH5 up-count compared point
#1001 : 9
EPWM_CH5 down-count compared point
#1010 : 10
EPWM_CH0 up-count free trigger compared point
#1011 : 11
EPWM_CH0 down-count free trigger compared point
#1100 : 12
EPWM_CH2 up-count free trigger compared point
#1101 : 13
EPWM_CH2 down-count free trigger compared point
#1110 : 14
EPWM_CH4 up-count free trigger compared point
#1111 : 15
EPWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN4 : EPWM_CH4 Trigger EADC Enable Bit
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH4 Trigger EADC function Disabled
#1 : 1
EPWM_CH4 Trigger EADC function Enabled
End of enumeration elements list.
TRGSEL5 : EPWM_CH5 Trigger EADC Source Select
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
EPWM_CH4 zero point
#0001 : 1
EPWM_CH4 period point
#0010 : 2
EPWM_CH4 zero or period point
#0011 : 3
EPWM_CH4 up-count compared point
#0100 : 4
EPWM_CH4 down-count compared point
#0101 : 5
EPWM_CH5 zero point
#0110 : 6
EPWM_CH5 period point
#0111 : 7
EPWM_CH5 zero or period point
#1000 : 8
EPWM_CH5 up-count compared point
#1001 : 9
EPWM_CH5 down-count compared point
#1010 : 10
EPWM_CH0 up-count free trigger compared point
#1011 : 11
EPWM_CH0 down-count free trigger compared point
#1100 : 12
EPWM_CH2 up-count free trigger compared point
#1101 : 13
EPWM_CH2 down-count free trigger compared point
#1110 : 14
EPWM_CH4 up-count free trigger compared point
#1111 : 15
EPWM_CH4 down-count free trigger compared point
End of enumeration elements list.
TRGEN5 : EPWM_CH5 Trigger EADC Enable Bit
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
EPWM_CH5 Trigger EADC function Disabled
#1 : 1
EPWM_CH5 Trigger EADC function Enabled
End of enumeration elements list.
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