Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x110 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0xC0 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC8 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
CAM Comparison Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AUP : Accept Unicast Packet\nThe AUP controls the unicast packet reception. If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC receives packet depends on the CAM comparison result
#1 : 1
EMAC receives all unicast packets
End of enumeration elements list.
AMP : Accept Multicast Packet\nThe AMP controls the multicast packet reception. If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC receives packet depends on the CAM comparison result
#1 : 1
EMAC receives all multicast packets
End of enumeration elements list.
ABP : Accept Broadcast Packet\nThe ABP controls the broadcast packet reception. If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC receives packet depends on the CAM comparison result
#1 : 1
EMAC receives all broadcast packets
End of enumeration elements list.
COMPEN : Complement CAM Comparison Enable Bit\nThe COMPEN controls the complement of the CAM comparison result. If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped. And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Complement CAM comparison result Disabled
#1 : 1
Complement CAM comparison result Enabled
End of enumeration elements list.
CMPEN : CAM Compare Enable Bit\nThe CMPEN controls the enable of CAM comparison function for destination MAC address recognition. If software wants to receive a packet with specific destination MAC address, configures the MAC address into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAM comparison function for destination MAC address recognition Disabled
#1 : 1
CAM comparison function for destination MAC address recognition Enabled
End of enumeration elements list.
CAM1 Most Significant Word Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Time Stamp Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEN : Time Stamp Function Enable Bit\nThis bit controls if the IEEE 1588 PTP time stamp function is enabled or not.\nSet this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
I EEE 1588 PTP time stamp function Disabled
#1 : 1
IEEE 1588 PTP time stamp function Enabled
End of enumeration elements list.
TSIEN : Time Stamp Counter Initialization Enable Bit\nSet this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter.\nAfter the load operation finished, Ethernet MAC controller clear this bit to low automatically.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time stamp counter initialization done
#1 : 1
Time stamp counter initialization Enabled
End of enumeration elements list.
TSMODE : Time Stamp Fine Update Enable Bit\nThis bit chooses the time stamp counter update mode.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time stamp counter is in coarse update mode
#1 : 1
Time stamp counter is in fine update mode
End of enumeration elements list.
TSUPDATE : Time Stamp Counter Time Update Enable Bit\nSet this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter.\nAfter the add operation finished, Ethernet MAC controller clear this bit to low automatically.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No action
#1 : 1
EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC
End of enumeration elements list.
TSALMEN : Time Stamp Alarm Enable Bit\nSet this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC
#1 : 1
Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC
End of enumeration elements list.
Time Stamp Counter Second Register
address_offset : 0x110 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEC : Time Stamp Counter Second\nThis register reflects the bit [63:32] value of 64-bit reference timing counter. This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
bits : 0 - 31 (32 bit)
access : read-only
Time Stamp Counter Sub Second Register
address_offset : 0x114 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUBSEC : Time Stamp Counter Sub-second\nThis register reflects the bit [31:0] value of 64-bit reference timing counter. This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
bits : 0 - 31 (32 bit)
access : read-only
Time Stamp Increment Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTINC : Time Stamp Counter Increment\nTime stamp counter increment value.\nIf TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value.
bits : 0 - 7 (8 bit)
access : read-write
Time Stamp Addend Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDEND : Time Stamp Counter Addend\nThis register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.\nIf TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, the EMAC increases accumulator with this 32-bit value in each HCLK. Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit value kept in register EMAC_TSINC.
bits : 0 - 31 (32 bit)
access : read-write
Time Stamp Update Second Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : Time Stamp Counter Second Update\nWhen TSIEN (EMAC_TSCTL[1]) is high, EMAC loads this 32-bit value to EMAC_TSSEC directly. When TSUPDATE (EMAC_TSCTL[3]) is high, the EMAC increases EMAC_TSSEC with this 32-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Time Stamp Update Sub Second Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBSEC : Time Stamp Counter Sub-second Update\nWhen TSIEN (EMAC_TSCTL[1]) is high, EMAC loads this 32-bit value to EMAC_TSSUBSEC directly. When TSUPDATE (EMAC_TSCTL[3]) is high, the EMAC increases EMAC_TSSUBSEC with this 32-bit value.
bits : 0 - 31 (32 bit)
access : read-write
Time Stamp Alarm Second Register
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEC : Time Stamp Counter Second Alarm\nTime stamp counter second part alarm value.\nThis value is only useful when ALMEN (EMAC_TSCTL[5]) is high. If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, the Ethernet MAC controller sets TSALMIF (EMAC_INTSTS[28]) high.
bits : 0 - 31 (32 bit)
access : read-write
Time Stamp Alarm Sub Second Register
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUBSEC : Time Stamp Counter Sub-second Alarm\nTime stamp counter sub-second part alarm value.\nThis value is only useful when ALMEN (EMAC_TSCTL[5]) is high. If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, the Ethernet MAC controller sets TSALMIF (EMAC_INTSTS[28]) high.
bits : 0 - 31 (32 bit)
access : read-write
CAM1 Least Significant Word Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM2 Most Significant Word Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM2 Least Significant Word Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM3 Most Significant Word Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM3 Least Significant Word Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM4 Most Significant Word Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM4 Least Significant Word Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM5 Most Significant Word Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM5 Least Significant Word Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM6 Most Significant Word Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM6 Least Significant Word Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAMxEN : CAM Entry x Enable Bit
The CAMxEN controls the validation of CAM entry x.
The CAM entry 13, 14 and 15 are for PAUSE control frame transmission. If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
CAM entry x Disabled
#1 : 1
CAM entry x Enabled
End of enumeration elements list.
CAM7 Most Significant Word Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM7 Least Significant Word Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM8 Most Significant Word Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM8 Least Significant Word Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM9 Most Significant Word Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM9 Least Significant Word Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM10 Most Significant Word Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM10 Least Significant Word Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM11 Most Significant Word Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM11 Least Significant Word Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM12 Most Significant Word Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM12 Least Significant Word Register
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM13 Most Significant Word Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM13 Least Significant Word Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM14 Most Significant Word Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM14 Least Significant Word Register
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAM0 Most Significant Word Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACADDR2 : MAC Address Byte 2
bits : 0 - 7 (8 bit)
access : read-write
MACADDR3 : MAC Address Byte 3
bits : 8 - 15 (8 bit)
access : read-write
MACADDR4 : MAC Address Byte 4
bits : 16 - 23 (8 bit)
access : read-write
MACADDR5 : MAC Address Byte 5\nThe CAMxM keeps the bit 47~16 of MAC address. The x can be the 0~14. The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.\nFor example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
bits : 24 - 31 (8 bit)
access : read-write
CAM15 Most Significant Word Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPCODE : OP Code Field of PAUSE Control Frame\nIn the PAUSE control frame, an op code field defined and is 0x0001.
bits : 0 - 15 (16 bit)
access : read-write
LENGTH : LENGTH Field of PAUSE Control Frame\nIn the PAUSE control frame, a LENGTH field defined and is 0x8808.
bits : 16 - 31 (16 bit)
access : read-write
CAM15 Least Significant Word Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPERAND : Pause Parameter\nIn the PAUSE control frame, an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused. The unit of the OPERAND is a slot time, the 512-bit time.
bits : 24 - 31 (8 bit)
access : read-write
Transmit Descriptor Link List Start Address Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDSA : Transmit Descriptor Link-list Start Address\nThe TXDSA keeps the start address of transmit descriptor link-list. If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the current transmit descriptor start address register (EMAC_CTXDSA). The TXDSA does not be updated by EMAC. During the operation, EMAC will ignore the bits [1:0] of TXDSA. This means that TX descriptors must locate at word boundary memory address.
bits : 0 - 31 (32 bit)
access : read-write
Receive Descriptor Link List Start Address Register
address_offset : 0x8C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDSA : Receive Descriptor Link-list Start Address\nThe RXDSA keeps the start address of receive descriptor link-list. If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current receive descriptor start address register (EMAC_CRXDSA). The RXDSA does not be updated by EMAC. During the operation, EMAC will ignore the bits [1:0] of RXDSA. This means that RX descriptors must locate at word boundary memory address.
bits : 0 - 31 (32 bit)
access : read-write
MAC Control Register
address_offset : 0x90 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXON : Frame Reception ON\nThe RXON controls the normal packet reception of EMAC. If the RXON is set to high, the EMAC starts the packet reception process, including the RX descriptor fetching, packet reception and RX descriptor modification.\nIt is necessary to finish EMAC initial sequence before enable RXON. Otherwise, the EMAC operation is undefined.\nIf the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet reception process after the current packet reception finished.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Packet reception process stopped
#1 : 1
Packet reception process started
End of enumeration elements list.
ALP : Accept Long Packet\nThe ALP controls the long packet, which packet length is greater than 1518 bytes, reception. If the ALP is set to high, the EMAC will accept the long packet.\nOtherwise, the long packet will be dropped.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Ethernet MAC controller dropped the long packet
#1 : 1
Ethernet MAC controller received the long packet
End of enumeration elements list.
ARP : Accept Runt Packet\nThe ARP controls the runt packet, which length is less than 64 bytes, reception. If the ARP is set to high, the EMAC will accept the runt packet.\nOtherwise, the runt packet will be dropped.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Ethernet MAC controller dropped the runt packet
#1 : 1
Ethernet MAC controller received the runt packet
End of enumeration elements list.
ACP : Accept Control Packet\nThe ACP controls the control frame reception. If the ACP is set to high, the EMAC will accept the control frame. Otherwise, the control frame will be dropped. It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Ethernet MAC controller dropped the control frame
#1 : 1
Ethernet MAC controller received the control frame
End of enumeration elements list.
AEP : Accept CRC Error Packet\nThe AEP controls the EMAC accepts or drops the CRC error packet. If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Ethernet MAC controller dropped the CRC error packet
#1 : 1
Ethernet MAC controller received the CRC error packet
End of enumeration elements list.
STRIPCRC : Strip CRC Checksum\nThe STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum. If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The 4 bytes CRC checksum is included in packet length calculation
#1 : 1
The 4 bytes CRC checksum is excluded in packet length calculation
End of enumeration elements list.
WOLEN : Wake on LAN Enable Bit\nThe WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode.\nIf incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller would generate a wakeup event to wake system up from Power-down mode.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up by Magic Packet function Disabled
#1 : 1
Wake-up by Magic Packet function Enabled
End of enumeration elements list.
TXON : Frame Transmission ON\nThe TXON controls the normal packet transmission of EMAC. If the TXON is set to high, the EMAC starts the packet transmission process, including the TX descriptor fetching, packet transmission and TX descriptor modification.\nIt is must to finish EMAC initial sequence before enable TXON. Otherwise, the EMAC operation is undefined.\nIf the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet transmission process after the current packet transmission finished.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Packet transmission process stopped
#1 : 1
Packet transmission process started
End of enumeration elements list.
NODEF : No Deferral\nThe NODEF controls the enable of deferral exceed counter. If NODEF is set to high, the deferral exceed counter is disabled. The NODEF is only useful while EMAC is operating on half duplex mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The deferral exceed counter Enabled
#1 : 1
The deferral exceed counter Disabled
End of enumeration elements list.
SDPZ : Send PAUSE Frame\nThe SDPZ controls the PAUSE control frame transmission.\nIf S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set. Then, set SDPZ to 1 enables the PAUSE control frame transmission.\nThe SDPZ is a self-clear bit. This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.\nIt is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PAUSE control frame transmission completed
#1 : 1
PAUSE control frame transmission Enabled
End of enumeration elements list.
SQECHKEN : SQE Checking Enable Bit\nThe SQECHKEN controls the enable of SQE checking. The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode. In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100M bps or full duplex mode.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode
#1 : 1
SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode
End of enumeration elements list.
FUDUP : Full Duplex Mode Selection\nThe FUDUP controls that if EMAC is operating on full or half duplex mode.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC operates in half duplex mode
#1 : 1
EMAC operates in full duplex mode
End of enumeration elements list.
RMIIRXCTL : RMII RX Control\nThe RMIIRXCTL control the receive data sample in RMII mode. It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
RMII RX control Disabled
#1 : 1
RMII RX control Enabled
End of enumeration elements list.
OPMODE : Operation Mode Selection\nThe OPMODE defines that if the EMAC is operating on 10M or 100M bps mode. The RST (EMAC_CTL[24]) would not affect OPMODE value.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC operates in 10Mbps mode
#1 : 1
EMAC operates in 100Mbps mode
End of enumeration elements list.
RMIIEN : RMII Mode Enable Bit\nThis bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface. The RST (EMAC_CTL[24]) would not affect RMIIEN value.\nNote: This field must keep 1.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Ethernet MAC controller RMII mode Disabled
#1 : 1
Ethernet MAC controller RMII mode Enabled
End of enumeration elements list.
RST : Software Reset\nThe RST implements a reset function to make the EMAC return default state. The RST is a self-clear bit. This means after the software reset finished, the RST will be cleared automatically. Enable RST can also reset all control and status registers, exclusive of the control bits RMIIEN (EMAC_CTL[22]), and OPMODE (EMAC_CTL[20]).\nThe EMAC re-initial is necessary after the software reset completed.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Software reset completed
#1 : 1
Software reset Enabled
End of enumeration elements list.
MII Management Data Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : MII Management Data\nThe DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command.
bits : 0 - 15 (16 bit)
access : read-write
MII Management Control and Address Register
address_offset : 0x98 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYREG : PHY Register Address\nThe PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command.
bits : 0 - 4 (5 bit)
access : read-write
PHYADDR : PHY Address\nThe PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
bits : 8 - 12 (5 bit)
access : read-write
WRITE : Write Command\nThe Write defines the MII management command is a read or write.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
MII management command is a read command
#1 : 1
MII management command is a write command
End of enumeration elements list.
BUSY : Busy Bit\nThe BUSY controls the enable of the MII management frame generation. If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates the MII management frame to external PHY through MII Management I/F. The BUSY is a self-clear bit. This means the BUSY will be cleared automatically after the MII management command finished.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
MII management command generation finished
#1 : 1
MII management command generation Enabled
End of enumeration elements list.
PREAMSP : Preamble Suppress\nThe PREAMSP controls the preamble field generation of MII management frame. If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Preamble field generation of MII management frame not skipped
#1 : 1
Preamble field generation of MII management frame skipped
End of enumeration elements list.
MDCON : MDC Clock ON\nThe MDC controls the MDC clock generation. If the MDCON is set to high, the MDC clock is turned on.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
MDC clock off
#1 : 1
MDC clock on
End of enumeration elements list.
FIFO Threshold Control Register
address_offset : 0x9C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFOTH : RXFIFO Low Threshold\nThe RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory. The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold. The low threshold is the half of high threshold always. During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to transfer frame data from RXFIFO to system memory. If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame data to system memory.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Depend on the burst length setting. If the burst length is 8 words, high threshold is 8 words, too
#01 : 1
RXFIFO high threshold is 64B and low threshold is 32B
#10 : 2
RXFIFO high threshold is 128B and low threshold is 64B
#11 : 3
RXFIFO high threshold is 192B and low threshold is 96B
End of enumeration elements list.
TXFIFOTH : TXFIFO Low Threshold\nThe TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO. The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold. The high threshold is the twice of low threshold always. During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO. If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data from system memory to TXFIFO.\nThe TXFIFOTH also defines when the TXMAC starts to transmit frame out to network. The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold during the transmission of the frame. If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
Undefined
#01 : 1
TXFIFO low threshold is 64B and high threshold is 128B
#10 : 2
TXFIFO low threshold is 80B and high threshold is 160B
#11 : 3
TXFIFO low threshold is 96B and high threshold is 192B
End of enumeration elements list.
BURSTLEN : DMA Burst Length\nThis defines the burst length of AHB bus cycle while EMAC accesses system memory.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
4 words
#01 : 1
8 words
#10 : 2
16 words
#11 : 3
16 words
End of enumeration elements list.
Transmit Start Demand Register
address_offset : 0xA0 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXST : Transmit Start Demand\nIf the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted. After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.\nThe EMAC_TXST is a write only register and read from this register is undefined.\nThe write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
bits : 0 - 31 (32 bit)
access : write-only
Receive Start Demand Register
address_offset : 0xA4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXST : Receive Start Demand\nIf the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted. After the S/W has prepared the new RX descriptor for frame reception, it must issue a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.\nThe EMAC_RXST is a write only register and read from this register is undefined.\nThe write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
bits : 0 - 31 (32 bit)
access : write-only
Maximum Receive Frame Control Register
address_offset : 0xA8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRFL : Maximum Receive Frame Length\nThe MRFL defines the maximum frame length for received frame. If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.\nIt is recommended that only use MRFL to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes.
bits : 0 - 15 (16 bit)
access : read-write
MAC Interrupt Enable Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIEN : Receive Interrupt Enable Bit\nThe RXIEN controls the RX interrupt generation.\nIf RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU. If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] is set and the corresponding bit of EMAC_INTEN is enabled. In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled. And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled
#1 : 1
RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled
End of enumeration elements list.
CRCEIEN : CRC Error Interrupt Enable Bit\nThe CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation. If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CRCEIF (EMAC_INTSTS[1]) is set.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled
#1 : 1
CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled
End of enumeration elements list.
RXOVIEN : Receive FIFO Overflow Interrupt Enable Bit\nThe RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation. If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled
#1 : 1
RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled
End of enumeration elements list.
LPIEN : Long Packet Interrupt Enable Bit\nThe LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation. If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF (EMAC_INTSTS[3]) is set.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled
#1 : 1
LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled
End of enumeration elements list.
RXGDIEN : Receive Good Interrupt Enable Bit\nThe RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation. If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXGDIF (EMAC_INTSTS[4]) is set.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled
#1 : 1
RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled
End of enumeration elements list.
ALIEIEN : Alignment Error Interrupt Enable Bit\nThe ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation. If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the ALIEIF (EMAC_INTSTS[5]) is set.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled
#1 : 1
ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled
End of enumeration elements list.
RPIEN : Runt Packet Interrupt Enable Bit\nThe RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation. If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RPIF (EMAC_INTSTS[6]) is set.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled
#1 : 1
RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled
End of enumeration elements list.
MPCOVIEN : Miss Packet Counter Overrun Interrupt Enable Bit\nThe MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation. If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MPCOVIF (EMAC_INTSTS[7]) is set.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled
#1 : 1
MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled
End of enumeration elements list.
MFLEIEN : Maximum Frame Length Exceed Interrupt Enable Bit\nThe MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation. If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled
#1 : 1
MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled
End of enumeration elements list.
DENIEN : DMA Early Notification Interrupt Enable Bit\nThe DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation. If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the DENIF (EMAC_INTSTS[9]) is set.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled
#1 : 1
TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled
End of enumeration elements list.
RDUIEN : Receive Descriptor Unavailable Interrupt Enable Bit\nThe RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation. If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RDUIF (EMAC_MIOSTA[10]) register is set.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled
#1 : 1
RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled
End of enumeration elements list.
RXBEIEN : Receive Bus Error Interrupt Enable Bit\nThe RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation. If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXBEIF (EMAC_INTSTS[11]) is set.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled
#1 : 1
RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled
End of enumeration elements list.
CFRIEN : Control Frame Receive Interrupt Enable Bit\nThe CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation. If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CFRIF (EMAC_INTSTS[14]) register is set.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled
#1 : 1
CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled
End of enumeration elements list.
WOLIEN : Wake on LAN Interrupt Enable Bit\nThe WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation. If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU. If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the WOLIF (EMAC_INTSTS[15]) is set.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled
#1 : 1
WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled
End of enumeration elements list.
TXIEN : Transmit Interrupt Enable Bit\nThe TXIEN controls the TX interrupt generation.\nIf TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU. If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled. In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled. And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled
#1 : 1
TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled
End of enumeration elements list.
TXUDIEN : Transmit FIFO Underflow Interrupt Enable Bit\nThe TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation. If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXUDIF (EMAC_INTSTS[17]) is set.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled
#1 : 1
TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled
End of enumeration elements list.
TXCPIEN : Transmit Completion Interrupt Enable Bit\nThe TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation. If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXCPIF (EMAC_INTSTS[18]) is set.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled
#1 : 1
TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled
End of enumeration elements list.
EXDEFIEN : Defer Exceed Interrupt Enable Bit\nThe EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation. If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the EXDEFIF (EMAC_INTSTS[19]) is set.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled
#1 : 1
EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled
End of enumeration elements list.
NCSIEN : No Carrier Sense Interrupt Enable Bit\nThe NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation. If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the NCSIF (EMAC_INTSTS[20]) is set.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled
#1 : 1
NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled
End of enumeration elements list.
TXABTIEN : Transmit Abort Interrupt Enable Bit\nThe TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation. If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXABTIF (EMAC_INTSTS[21]) is set.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled
#1 : 1
TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled
End of enumeration elements list.
LCIEN : Late Collision Interrupt Enable Bit\nThe LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation. If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the LCIF (EMAC_INTSTS[22]) is set.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled
#1 : 1
LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled
End of enumeration elements list.
TDUIEN : Transmit Descriptor Unavailable Interrupt Enable Bit\nThe TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation. If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TDUIF (EMAC_INTSTS[23]) is set.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled
#1 : 1
TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled
End of enumeration elements list.
TXBEIEN : Transmit Bus Error Interrupt Enable Bit\nThe TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation. If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU. If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXBEIF (EMAC_INTSTS[24]) is set.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled
#1 : 1
TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled
End of enumeration elements list.
TSALMIEN : Time Stamp Alarm Interrupt Enable Bit\nThe TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation. If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the EMAC generates the TX interrupt to CPU. If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the TXTSALMIF (EMAC_INTEN[28]) is set.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled
#1 : 1
TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled
End of enumeration elements list.
MAC Interrupt Status Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIF : Receive Interrupt\nThe RXIF indicates the RX interrupt status.\nIf RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates the EMAC generates RX interrupt to CPU. If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.\nThe RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1]. In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in EMAC_INTEN[15:1] is also enabled, the RXIF will be high.\nBecause the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled
#1 : 1
At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in EMAC_INTEN[15:1] is enabled, too
End of enumeration elements list.
CRCEIF : CRC Error Interrupt\nThe CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped. If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and CRCEIF will not be set.\nIf the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high. Write 1 to this bit clears the CRCEIF status.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The frame does not incur CRC error
#1 : 1
The frame incurred CRC error
End of enumeration elements list.
RXOVIF : Receive FIFO Overflow Interrupt\nThe RXOVIF high indicates the RXFIFO overflow occurred during packet reception. While the RXFIFO overflow occurred, the EMAC drops the current receiving packer. If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, the RXFIFOTH of FFTCR register, to higher level.\nIf the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high. Write 1 to this bit clears the RXOVIF status.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No RXFIFO overflow occurred during packet reception
#1 : 1
RXFIFO overflow occurred during packet reception
End of enumeration elements list.
LPIF : Long Packet Interrupt Flag\nThe LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped. If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.\nIf the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high. Write 1 to this bit clears the LPIF status.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The incoming frame is not a long frame or S/W wants to receive a long frame
#1 : 1
The incoming frame is a long frame and dropped
End of enumeration elements list.
RXGDIF : Receive Good Interrupt\nThe RXGDIF high indicates the frame reception has completed.\nIf the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high. Write 1 to this bit clears the RXGDIF status.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The frame reception has not complete yet
#1 : 1
The frame reception has completed
End of enumeration elements list.
ALIEIF : Alignment Error Interrupt\nThe ALIEIF high indicates the length of the incoming frame is not a multiple of byte. If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high. Write 1 to this bit clears the ALIEIF status.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The frame length is a multiple of byte
#1 : 1
The frame length is not a multiple of byte
End of enumeration elements list.
RPIF : Runt Packet Interrupt\nThe RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped. If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.\nIf the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high. Write 1 to this bit clears the RPIF status.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The incoming frame is not a short frame or S/W wants to receive a short frame
#1 : 1
The incoming frame is a short frame and dropped
End of enumeration elements list.
MPCOVIF : Missed Packet Counter Overrun Interrupt Flag\nThe MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow. If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high. Write 1 to this bit clears the MPCOVIF status.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MPCNT has not rolled over yet
#1 : 1
The MPCNT has rolled over yet
End of enumeration elements list.
MFLEIF : Maximum Frame Length Exceed Interrupt Flag\nThe MFLEIF high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped. If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high. Write 1 to this bit clears the MFLEIF status.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The length of the incoming packet does not exceed the length limitation configured in DMARFC
#1 : 1
The length of the incoming packet has exceeded the length limitation configured in DMARFC
End of enumeration elements list.
DENIF : DMA Early Notification Interrupt\nThe DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.\nIf the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high. Write 1 to this bit clears the DENIF status.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The LENGTH field of incoming packet has not received yet
#1 : 1
The LENGTH field of incoming packet has received
End of enumeration elements list.
RDUIF : Receive Descriptor Unavailable Interrupt\nThe RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state. Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.\nIf the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high. Write 1 to this bit clears the RDUIF status.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
RX descriptor is available
#1 : 1
RX descriptor is unavailable
End of enumeration elements list.
RXBEIF : Receive Bus Error Interrupt\nThe RXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through RXDMA during packet reception process. Reset EMAC is recommended while RXBEIF status is high.\nIf the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high. Write 1 to this bit clears the RXBEIF status.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ERROR response is received
#1 : 1
ERROR response is received
End of enumeration elements list.
CFRIF : Control Frame Receive Interrupt\nThe CFRIF high indicates EMAC receives a flow control frame. The CFRIF only available while EMAC is operating on full duplex mode.\nIf the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high. Write 1 to this bit clears the CFRIF status.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The EMAC does not receive the flow control frame
#1 : 1
The EMAC receives a flow control frame
End of enumeration elements list.
WOLIF : Wake on LAN Interrupt Flag\nThe WOLIF high indicates EMAC receives a Magic Packet. The CFRIF only available while system is in Power-down mode and WOLEN is set high.\nIf the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high. Write 1 to this bit clears the WOLIF status.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The EMAC does not receive the Magic Packet
#1 : 1
The EMAC receives a Magic Packet
End of enumeration elements list.
TXIF : Transmit Interrupt\nThe TXIF indicates the TX interrupt status.\nIf TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates the EMAC generates TX interrupt to CPU. If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.\nThe TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17]. In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit in EMAC_INTEN[28:17] is also enabled, the TXIF will be high. Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled
#1 : 1
At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit in EMAC_INTEN[28:17] is enabled, too
End of enumeration elements list.
TXUDIF : Transmit FIFO Underflow Interrupt\nThe TXUDIF high indicates the TXFIFO underflow occurred during packet transmission. While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention. If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXFIFOTH of FFTCR register, to higher level.\nIf the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXUDIF status.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TXFIFO underflow occurred during packet transmission
#1 : 1
TXFIFO underflow occurred during packet transmission
End of enumeration elements list.
TXCPIF : Transmit Completion Interrupt\nThe TXCPIF indicates the packet transmission has completed correctly.\nIf the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXCPIF status.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The packet transmission not completed
#1 : 1
The packet transmission has completed
End of enumeration elements list.
EXDEFIF : Defer Exceed Interrupt\nThe EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode. The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC is operating on half-duplex mode.\nIf the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high. Write 1 to this bit clears the EXDEFIF status.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps)
#1 : 1
Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps)
End of enumeration elements list.
NCSIF : No Carrier Sense Interrupt\nThe NCSIF high indicates the MII I/F signal CRS does not active at the start of or during the packet transmission. The NCSIF is only available while EMAC is operating on half-duplex mode. If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high. Write 1 to this bit clears the NCSIF status.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
CRS signal actives correctly
#1 : 1
CRS signal does not active at the start of or during the packet transmission
End of enumeration elements list.
TXABTIF : Transmit Abort Interrupt\nThe TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted. The transmission abort is only available while EMAC is operating on half-duplex mode.\nIf the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXABTIF status.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Packet does not incur 16 consecutive collisions during transmission
#1 : 1
Packet incurred 16 consecutive collisions during transmission
End of enumeration elements list.
LCIF : Late Collision Interrupt\nThe LCIF high indicates the collision occurred in the outside of 64 bytes collision window. This means after the 64 bytes of a frame has been transmitted out to the network, the collision still occurred. The late collision check will only be done while EMAC is operating on half-duplex mode. If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high. Write 1 to this bit clears the LCIF status.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No collision occurred in the outside of 64 bytes collision window
#1 : 1
Collision occurred in the outside of 64 bytes collision window
End of enumeration elements list.
TDUIF : Transmit Descriptor Unavailable Interrupt\nThe TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state. Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.\nIf the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high. Write 1 to this bit clears the TDUIF status.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
TX descriptor is available
#1 : 1
TX descriptor is unavailable
End of enumeration elements list.
TXBEIF : Transmit Bus Error Interrupt\nThe TXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through TXDMA during packet transmission process. Reset EMAC is recommended while TXBEIF status is high.\nIf the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high. Write 1 to this bit clears the TXBEIF status.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ERROR response is received
#1 : 1
ERROR response is received
End of enumeration elements list.
TSALMIF : Time Stamp Alarm Interrupt\nThe TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and EMAC_TSSUBSEC register value equals to register EMAC_ALMSUBSEC.\nIf TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high. Write 1 to this bit clears the TSALMIF status.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC
#1 : 1
EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC
End of enumeration elements list.
MAC General Status Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CFR : Control Frame Received\nThe CFRIF high indicates EMAC receives a flow control frame. The CFRIF only available while EMAC is operating on full duplex mode.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The EMAC does not receive the flow control frame
#1 : 1
The EMAC receives a flow control frame
End of enumeration elements list.
RXHALT : Receive Halted\nThe RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next normal packet reception process will go on
#1 : 1
Next normal packet reception process will be halted
End of enumeration elements list.
RXFFULL : RXFIFO Full\nThe RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The RXFIFO is not full
#1 : 1
The RXFIFO is full and the following incoming packet will be dropped
End of enumeration elements list.
COLCNT : Collision Count
The COLCNT indicates that how many collisions occurred consecutively during a packet transmission. If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 4h0 and bit TXABTIF will be set to 1.
bits : 4 - 7 (4 bit)
access : read-write
DEF : Deferred Transmission\nThe DEF high indicates the packet transmission has deferred once. The DEF is only available while EMAC is operating on half-duplex mode.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Packet transmission does not defer
#1 : 1
Packet transmission has deferred once
End of enumeration elements list.
TXPAUSED : Transmission Paused\nThe TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next normal packet transmission process will go on
#1 : 1
Next normal packet transmission process will be paused
End of enumeration elements list.
SQE : Signal Quality Error\nThe SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode. The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC is operating on 10Mbps half-duplex mode.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SQE error found at end of packet transmission
#1 : 1
SQE error found at end of packet transmission
End of enumeration elements list.
TXHALT : Transmission Halted\nThe TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Next normal packet transmission process will go on
#1 : 1
Next normal packet transmission process will be halted
End of enumeration elements list.
RPSTS : Remote Pause Status\nThe RPSTS indicates that remote pause counter down counting actives.\nAfter Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause counter down counting. When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet transmission until the down counting done.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Remote pause counter down counting done
#1 : 1
Remote pause counter down counting actives
End of enumeration elements list.
Missed Packet Count Register
address_offset : 0xB8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPCNT : Miss Packet Count\nThe MPCNT indicates the number of packets that were dropped due to various types of receive errors. The following type of receiving error makes missed packet counter increase:\nIncoming packet is incurred RXFIFO overflow.\nIncoming packet is dropped due to RXON is disabled.\nIncoming packet is incurred CRC error.
bits : 0 - 15 (16 bit)
access : read-write
MAC Receive Pause Count Register
address_offset : 0xBC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RPCNT : MAC Receive Pause Count\nThe RPCNT keeps the OPERAND field of the PAUSE control frame. It indicates how many slot time (512-bit time) the TX of EMAC will be paused.
bits : 0 - 15 (16 bit)
access : read-only
CAM0 Least Significant Word Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACADDR0 : MAC Address Byte 0
bits : 16 - 23 (8 bit)
access : read-write
MACADDR1 : MAC Address Byte 1\nThe CAMxL keeps the bit 15~0 of MAC address. The x can be the 0~14. The register pair {EMAC_CAMxM, EMAC_CAMxL} represents a CAM entry and keeps a MAC address.\nFor example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
bits : 24 - 31 (8 bit)
access : read-write
DMA Receive Frame Status Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFLT : Receive Frame LENGTH\nThe RXFLT keeps the LENGTH field of each incoming Ethernet packet. If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt. And, the content of LENGTH field will be stored in RXFLT.
bits : 0 - 15 (16 bit)
access : read-write
Current Transmit Descriptor Start Address Register
address_offset : 0xCC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTXDSA : Current Transmit Descriptor Start Address\nThe CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently. The CTXDSA is read only and write to this register has no effect.
bits : 0 - 31 (32 bit)
access : read-only
Current Transmit Buffer Start Address Register
address_offset : 0xD0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTXBSA : Current Transmit Buffer Start Address\nThe CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently. The CTXBSA is read only and write to this register has no effect.
bits : 0 - 31 (32 bit)
access : read-only
Current Receive Descriptor Start Address Register
address_offset : 0xD4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRXDSA : Current Receive Descriptor Start Address\nThe CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently. The CRXDSA is read only and write to this register has no effect.
bits : 0 - 31 (32 bit)
access : read-only
Current Receive Buffer Start Address Register
address_offset : 0xD8 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRXBSA : Current Receive Buffer Start Address\nThe CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently. The CRXBSA is read only and write to this register has no effect.
bits : 0 - 31 (32 bit)
access : read-only
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