SPIM_CTL0 (CTL0)

SPIM_RX0 (RX0)

SPIM_RX1 (RX1)

SPIM_RX2 (RX2)

SPIM_RX3 (RX3)

SPIM_TX0 (TX0)

SPIM_TX1 (TX1)

SPIM_TX2 (TX2)

SPIM_TX3 (TX3)

SPIM_SRAMADDR (SRAMADDR)

SPIM_DMACNT (DMACNT)

SPIM_FADDR (FADDR)

SPIM_KEY1 (KEY1)

SPIM_CTL1 (CTL1)

SPIM_KEY2 (KEY2)

SPIM_DMMCTL (DMMCTL)

SPIM_CTL2 (CTL2)

SPIM_RXCLKDLY (RXCLKDLY)

CIPHOFF : Cipher Disable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BALEN : Balance the AHB Control Time Between Cipher Enable and Disable Control\nWhen cipher is enabled, the AHB control signal will delay some time caused by the encoding or decoding calculation. Therefore, if set BALEN to 1, it will make the AHB signal processing time with cipher disabled be equal to that with cipher enabled.\nNote: Only useful when cipher is disabled.
bits : 2 - 2 (1 bit)
access : read-write

B4ADDREN : 4-byte Address Mode Enable Bit\nNote: Used for DMA write mode, DMA read mode, and DMM mode.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IEN : Interrupt Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IF : Interrupt Flag\nWrite Operation:
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DWIDTH : Transmit/Receive Bit Length\nThis specifies how many bits are transmitted/received in one transmit/receive transaction.\nNote1: Only used for normal I/O mode.\nNote2: Only 8, 16, 24, and 32 bits are allowed. Other bit length will result in incorrect transfer.
bits : 8 - 12 (5 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BURSTNUM : Transmit/Receive Burst Number\nThis field specifies how many transmit/receive transactions should be executed continuously in one transfer.\nNote: Only used for normal I/O Mode.
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

QDIODIR : SPI Interface Direction Select for Quad/Dual Mode Note: Only used for normal I/O mode.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPITV : Suspend Interval Note: Only used for normal I/O mode.
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITMODE : SPI Interface Bit Mode\nNote: Only used for normal I/O mode.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OPMODE : SPI Function Operation Mode Note1: After using Normal I/O mode of SPI Flash controller to program the content of external SPI Flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). Note2: In DMA write mode, hardware will send just one page program command per operation. Users must take care of cross-page cases. After using DMA write mode of SPI Flash controller to program the content of external SPI Flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid). Note3: For external SPI Flash with 32 Mbytes, access address range of external SPI Flash address is from 0x00000000 to 0x01FFFFFF when using Normal I/O mode, DMA write mode, and DMA read mode to write/read external SPI Flash data. Please user check size of used SPI Flash component to know access address range of external SPI Flash. Note4: For external SPI Flash with 32 Mbytes, access address range of external SPI Flash address is from 0x08000000 to 0x09FFFFFF when using Direct Memory mapping mode (DMM mode) to read external SPI Flash data. Please user check size of used SPI Flash component to know access address range of external SPI Flash.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMDCODE : Page Program Command Code (Note4) The Others command codes are Reserved. The DTR/DDR read commands '0x0D,0xBD,0xED' improves throughput by transferring address and data on both the falling and rising edge of SPI Flash clock (SPIM_CLK). It is similar to those commands '0x0B, 0xBB, 0xEB' but allows transfer of address and data on rising edge and falling edge of SPI Flash output clock. (Note2) Note1: Quad mode of SPI Flash must be enabled first by normal I/O mode before using quad page program/quad read commands. Note2: See SPI Flash specifications for support items. Note3: For TYPE_1, TYPE_2, and TYPE_3 of page program command code, refer to Figure 6.223, Figure 6.224, and Figure 6.225. Note4: Please disable 'continuous read mode' and 'burst wrap mode' before DMA write mode of SPI Flash controller is used to program data of external SPI Flash. After using DMA write mode of SPI Flash controller to program the content of external SPI Flash, please set CDINVAL(SPIM_CTL1[3]) to 0x1 (Set all cache data to be invalid).
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDAT : Data Receive Register The Data Receive Registers hold the received data of the last executed transfer. Number of valid RX registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, received data are held in the most significant RXDAT register first. Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, received data are held in the least significant byte of RXDAT register first. In a byte, received data are held in the most significant bit of RXDAT register first.
bits : 0 - 31 (32 bit)
access : read-only

TXDAT : Data Transmit Register The Data Transmit Registers hold the data to be transmitted in next transfer. Number of valid TXDAT registers is specified in SPIM_CTL0[BURSTNUM]. If BURSTNUM 0, data are transmitted in the most significant TXDAT register first. Number of valid-bit is specified in SPIM_CTL0[DWIDTH]. If DWIDTH is 16, 24, or 32, data are transmitted in the least significant byte of TXDAT register first. In a byte, data are transmitted in the most significant bit of TXDAT register first.
bits : 0 - 31 (32 bit)
access : read-write

ADDR : SRAM Memory Address\nFor DMA Read mode, this is the destination address for DMA transfer.\nFor DMA Write mode, this is the source address for DMA transfer.\nNote: This address must be word-aligned.
bits : 0 - 31 (32 bit)
access : read-write

DMACNT : DMA Transfer Byte Count Register\nIt indicates the transfer length for DMA process. \nNote1: The unit for counting is byte.\nNote2: The number must be the multiple of 4.\nNote3: Please check specification of used SPI Flash to know maximum byte length of page program.
bits : 0 - 23 (24 bit)
access : read-write

ADDR : SPI Flash Address Register For DMA Read mode, this is the source address for DMA transfer. For DMA Write mode, this is the destination address for DMA transfer. Note1: This address must be word-aligned. Note2: For external SPI Flash with 32 Mbytes, the value of this SPI Flash address register 'ADDR' is from 0x00000000 to 0x01FFFFFF when using DMA write mode and DMA read mode to write/read external SPI Flash data. Please user check size of used SPI Flash component to know access address range of external SPI Flash.
bits : 0 - 31 (32 bit)
access : read-write

KEY1 : Cipher Key1 Register This is the KEY1 data for cipher function. Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. KEY1 0x0000_0000 and KEY20x0000_0000), cipher encryption/decryption is enabled.
bits : 0 - 31 (32 bit)
access : write-only

SPIMEN : Go and Busy Status\nWrite Operation:\nNote: All registers should be set before writing 1 to the SPIMEN bit. When a transfer is in progress, user should not write to any register of this peripheral.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACHEOFF : Cache Memory Function Disable Bit\nNote: When CCM mode is enabled, the cache function will be disable by hardware automatically. When CCM mode is disabled, the cache function can be enable or disable by user.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCMEN : CCM (Core Coupled Memory) Mode Enable Bit\nNote1: When CCM mode is enabled, the cache function will be disable by hardware automatically. When CCM mode is disabled, the cache function can be enabled or disabled by user.\nNote2: When CCM mode is disabled, user accesses the core coupled memory by bus master. In this case, the SPI Flash controller will send error response via HRESP bus signal to bus master.\nNote3: When CCM mode needs to be enabled, user sets CCMEN to 1 and needs to read this register to show the current hardware status. When reading data of CCMEN is 1, MCU can start to read data from CCM memory space or write data to CCM memory space.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CDINVAL : Cache Data Invalid Enable Bit\nWrite Operation:\nRead Operation: No effect\nNote: When SPI Flash memory is page erasing or whole Flash erasing, please set CDINVAL to 0x1. After using normal I/O mode or DMA write mode of SPI Flash controller to program or erase the content of external SPI Flash, please set CDINVAL to 0x1.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SS : Slave Select Active Enable Bit Note: This interface can only drive one device/slave at a given time. Therefore, the slave selects of the selected device must be set to its active level before starting any read or write transfer. Functional description of SSACTPOL(SPIM_CTL1[5]) and SS is shown in Table 6.222.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SSACTPOL : Slave Select Active Level It defines the active level of device/slave select signal (SPIM_SS), as shown in Table 6.222.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IDLETIME : Idle Time Interval\nIn DMM mode, IDLETIME is set to control the minimum idle time between two SPI Flash accesses.
bits : 8 - 11 (4 bit)
access : read-write

DIVIDER : Clock Divider Register The value in this field is the frequency divider of the AHB clock (HCLK) to generate the serial SPI output clock 'SCLK' on the output SPIM_CLK pin. The desired frequency is obtained according to the following equation: Note1: When set DIVIDER to zero, the frequency of SPIM_CLK will be equal to the frequency of HCLK. Note2: SCLK is serial SPI output clock. Note3: Please check the specification of the used SPI Flash component to decide the frequency of SPI Flash clock. Note4: For DTR/DDR read commands '0x0D, 0xBD, 0xED', the setting values of DIVIDER are only all multiples of 2. For example, 1,2,4,8,16,32,...
bits : 16 - 31 (16 bit)
access : read-write

KEY2 : Cipher Key2 Register This is the KEY2 data for cipher function. Note1: If there is not any KEY1(SPIM_KEY1[31:0]) or KEY2(SPIM_KEY2[31:0]) (KEY1 is 0x0000_0000 or KEY2 is 0x0000_0000), the cipher function will be disabled automatically. Note2: When CIPHOFF(SPIM_CTL0[0]) is 0, both of KEY1(SPIM_KEY1[31:0]) and KEY2(SPIM_KEY2[31:0]) do not equal to 0x0000_0000 (i.e. KEY1 0x0000_0000 and KEY20x0000_0000), cipher encryption/decryption is enabled.
bits : 0 - 31 (32 bit)
access : write-only

CRMDAT : Mode Bits Data for Continuous Read Mode (or Performance Enhance Mode) (Only for Direct Memory Mapping Mode)\nSet the mode bits data for continuous read mode (or performance enhance mode).\nWhen setting this mode bits currently (Note1) and set CREN(SPIM_DMMCTL[25]), this reduces the command phase by eight clocks and allows the read address to be immediately entered after SPIM_SS asserted to active. (Note1)\nNote1: Please check the used SPI Flash specification to know the setting value of this mode bits data, and different SPI Flash vendor may use different setting values.\nNote2: CRMDAT needs to be used with CREN(SPIM_DMMCTL[25]).
bits : 8 - 15 (8 bit)
access : read-write

DESELTIM : SPI Flash Deselect Time (Only for Direct Memory Mapping Mode) Set the minimum time width of SPI Flash deselect time (i.e. Minimum SPIM_SS deselect time), as shown in Figure 6.2211. (1) Cache function disable: Note3: Please check the used SPI Flash specification to know the setting value of this register, and different SPI Flash vendor may use different setting values.
bits : 16 - 20 (5 bit)
access : read-write

BWEN : 16 Bytes Burst Wrap Mode Enable Bit (Only for Direct Memory Mapping Mode, Cache Enable, and Read Command Code '0xEB, and 0xE7')\nIn direct memory mapping mode, both of quad read commands '0xEB' and '0xE7' support burst wrap mode for cache application and performance enhance. For cache application, the burst wrap mode can be used to fill the cache line quickly (In this SPI Flash controller, use cache data line with 16 bytes size). For performance enhance with direct memory mapping mode and cache enable, when cache data is miss, the burst wrap mode can let MCU get the required SPI Flash data quickly.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CREN : Continuous Read Mode Enable Bit (Only for Direct Memory Mapping Mode, Read Command Codes 0xBB, 0xEB, 0xE7, 0x0D, 0xBD, 0xED)\nFor read operations of SPI Flash, commands of fast read quad I/O (0xEB), word read quad I/O (0xE7), fast read dual I/O (0xBB), DTR/DDR fast read (0x0D), DTR/DDR fast read dual I/O (0xBD), and DTR/DDR fast read quad I/O (0xED) can further reduce command overhead through setting the 'continuous read mode' bits (8 bits) after the input address data.\nNote: When using function of continuous read mode and setting USETEN (SPIM_CTL2[16]) to 1, CRMDAT(SPIM_DMMCTL[15:8]) must be set by used SPI Flash specifications. When using function of continuous read mode and setting USETEN(SPIM_CTL2[16]) to 0, CRMDAT(SPIM_DMMCTL[15:8]) is set to value 0x20.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UACTSCLK : User Sets SPI Flash Active SCLK Time (Only for Direct Memory Mapping Mode, DMA Write Mode, and DMA Read Mode)\nNote: When user wants to set ACTSCLKT(SPIM_DMMCTL[31:28]) manually, please set UACTSCLK to 1.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACTSCLKT : SPI Flash Active SCLK Time (Only for Direct Memory Mapping Mode, DMA Write Mode, and DMA Read Mode) The bits set time interval between SPIM SS active edge and the position edge of the first serial SPI output clock, as shown in Figure 6.2211.. Note2: SCLK is SPI output clock Note3: Please check the used SPI Flash specification to know the setting value of this register, and different SPI Flash vendor may use different setting values.
bits : 28 - 31 (4 bit)
access : read-write

USETEN : User Set Value Enable Bit (Only for Direct Memory Mapping Mode and DMA Read Mode with Read Commands 0x03,0x0B,0x3B,0xBB,0xEB,0xE7)\nFor DTR/DDR command codes 0x0D, 0xBD, and 0xED, please set USETEN to 0x1.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DTRMPOFF : Mode Phase OFF for DTR/DDR Command Codes 0x0D, 0xBD, and 0xED (Only for Direct Memory Mapping Mode and DMA Read Mode)\nNote: Please check the used SPI Flash specification to know the mode cycle number (or performance enhance cycle number) for DTR/DDR command codes 0x0D, 0xBD, and 0xED.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DCNUM : Dummy Cycle Number (Only for Direct Memory Mapping Mode and DMA Read Mode)\nSet number of dummy cycles\n(1) For non-DTR/non-DDR command codes 0x03, 0x0B, 0x3B, 0xBB, 0xEB, and 0xE7:\nFor command codes 0x0B, 0x3B, 0xEB, and 0xE7, user only set DCNUM to dummy cycle number by used SPI Flash specification.\n\n(2) For DTR/DDR command codes 0x0D, 0xBD, and 0xED:\nuser sets DCNUM to dummy cycle number and DTRMPOFF(SPIM_CTL2[20]) by used SPI Flash specification.\nNote: Number of dummy cycles depends on the frequency of SPI output clock, SPI Flash vendor, and read command types. Please check the used SPI Flash specification to know the setting value of this number of dummy cycles.
bits : 24 - 28 (5 bit)
access : read-write

DWDELSEL : SPI Flash Deselect Time Interval of DMA Write Mode (for DMA Write Mode Only)\nThe bits set the deselect time interval of SPI Flash (i.e. time interval of inactive level of SPIM_SS) when SPI Flash controller operates on DMA write mode. (Note1)
bits : 0 - 7 (8 bit)
access : read-write

PHDELSEL : SPI Flash Phase Delay Time (for DMA Write Mode, DMA Read Mode)\nThe bits set phase delay time between command data phase, address data phase, and dummy cycle phase, where SPI Flash controller will send those phase data to external SPI Flash.
bits : 8 - 15 (8 bit)
access : read-write

RDDLYSEL : Sampling Clock Delay Selection for Received Data (for Normal I/O Mode, DMA Rread Mode, DMA Write Mode, and Direct Memory Mapping Mode)\nDetermine the number of inserted delay cycles. Used to adjust the sampling clock of received data to latch the correct data.\n0x0: No delay. (Default)\n0x1: Delay 1 SPI Flash clock.\n0x2: Delay 2 SPI Flash clocks.\n0x3: Delay 3 SPI Flash clocks.\n...\n0x7: Delay 7 SPI Flash clocks\nNote: The manufacturer or device ID of external SPI Flash component can be used to determine the correct setting value of RDDLYSEL. An example is given as follows.\nFor example, the manufacturer ID and device ID of external SPI Flash for some vendor are 0xEF and 0x1234 separately. First, set RDDLYSEL to 0x0, and use read manufacturer id/device id command to read the manufacturer id of external SPI Flash by using normal I/O mode (the manufacturer id is 0xEF (1110_1111) in this example).\nIf the manufacturer ID which reads from external SPI Flash is 0xF7 (1111_0111), it denotes that manufacturer id is shifted the right by 1 bit and most significant bit (MSB) of manufacturer id is assigned to 1. According to manufacturer id reads from external SPI Flash, RDDLYSEL needs to be set to 0x1 to receive SPI Flash data correctly.
bits : 16 - 18 (3 bit)
access : read-write

RDEDGE : Sampling Clock Edge Selection for Received Data (for Normal I/O Mode, DMA Read Mode, DMA Write Mode, and Direct Memory Mapping Mode)
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.