EHCVNR

UCMDR

USTSR

UIENR

UFINDR

UPFLBAR

UCALAR

UASSTR

EHCSPR

UCFGR

UPSCR0

UPSCR1

EHCCPR

USBPCR0

USBPCR1

CRLEN : Capability Registers Length\nThis register is used as an offset to add to register base to find the beginning of the Operational Register Space.
bits : 0 - 7 (8 bit)
access : read-only

VERSION : Host Controller Interface Version Number\nThis is a two-byte register containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision.
bits : 16 - 31 (16 bit)
access : read-only

RUN : Run/Stop (R/W)\nWhen set to a 1, the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to a 1. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears the Run bit. The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state. Software must not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). Doing so will yield undefined results.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCRST : Host Controller Reset (HCRESET) (R/W)\nThis control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.\nWhen software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.\nAll operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s), with the side effects. Software must reinitialize the host controller in order to return the host controller to an operational state.\nThis bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.\nSoftware should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.
bits : 1 - 1 (1 bit)
access : read-write

FLSZ : Frame List Size (R/W or RO)\nThis field is R/W only if Programmable Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the size of the frame list. The size the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index. Values mean:
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PSEN : Periodic Schedule Enable (R/W)\nThis bit controls whether the host controller skips processing the Periodic Schedule. Values mean:
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ASEN : Asynchronous Schedule Enable (R/W)\nThis bit controls whether the host controller skips processing the Asynchronous Schedule. Values mean:
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IAAD : Interrupt on Asynchronous Advance Doorbell (R/W)\nThis bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell.\nWhen the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Asynchronous Advance status bit in the USBSTS register. If the Interrupt on Asynchronous Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.\nThe host controller sets this bit to a zero after it has set the Interrupt on Asynchronous Advance status bit in the USBSTS register to a one.\nSoftware should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results.
bits : 6 - 6 (1 bit)
access : read-write

ITC : Interrupt Threshold Control (R/W)\nThis field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value Maximum Interrupt Interval\nAny other value in this register yields undefined results.\nSoftware modifications to this bit while HCHalted bit is equal to zero results in undefined behavior.
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBINT : USB Interrupt (USBINT) (R/WC)\nThe Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set.\nThe Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes).
bits : 0 - 0 (1 bit)
access : read-write

UERRINT : USB Error Interrupt (USBERRINT) (R/WC)\nThe Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set.
bits : 1 - 1 (1 bit)
access : read-write

PCD : Port Change Detect (R/WC)\nThe Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Change being set to a one after system software has relinquished ownership of a connected port by writing a one to a port's Port Owner bit.\nThis bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force port resume, over-current change, enable/disable change and connect status change).
bits : 2 - 2 (1 bit)
access : read-write

FLR : Frame List Rollover (R/WC)\nThe Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
bits : 3 - 3 (1 bit)
access : read-write

HSERR : Host System Error (R/WC)\nThe Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module.
bits : 4 - 4 (1 bit)
access : read-write

IAA : Interrupt on Asynchronous Advance (R/WC)\nSystem software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Asynchronous Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.
bits : 5 - 5 (1 bit)
access : read-write

HCHalted : HCHalted (Read Only)\nThis bit is a zero whenever the Run/Stop bit is a one. The Host Controller sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error).
bits : 12 - 12 (1 bit)
access : read-only

RECLA : Reclamation (Read Only)\nThis is a read-only status bit, which is used to detect an empty asynchronous schedule.
bits : 13 - 13 (1 bit)
access : read-only

PSS : Periodic Schedule Status (Read Only)\nThe bit reports the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).
bits : 14 - 14 (1 bit)
access : read-only

ASS : Asynchronous Schedule Status (Read Only)\nThe bit reports the current real status of the Asynchronous Schedule. If this bit is a zero then the status of them Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).
bits : 15 - 15 (1 bit)
access : read-only

USBIEN : USB Interrupt Enable or Disable Bit\nWhen this bit is a one, and the USBINT bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UERRIEN : USB Error Interrupt Enable or Disable Bit\nWhen this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the host t controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCIEN : Port Change Interrupt Enable or Disable Bit\nWhen this bit is a one, and the Port Change Detect bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FLREN : Frame List Rollover Enable or Disable Bit\nWhen this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HSERREN : Host System Error Enable or Disable Bit\nWhen this bit is a one, and the Host System Error Status bit in the USBSTS register is a one, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IAAEN : Interrupt on Asynchronous Advance Enable or Disable Bit\nWhen this bit is a one, and the Interrupt on Asynchronous Advance bit in the USBSTS register is a one, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Asynchronous Advance bit.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FI : Frame Index The value in this register increment at the end of each time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register. FLSZ (UCMDR[3:2] Number Elements N 0x0 1024 12 0x1 512 11 0x2 256 10 0x3 Reserved
bits : 0 - 13 (14 bit)
access : read-write

BADDR : Base Address\nThese bits correspond to memory address signals [31:12], respectively.
bits : 12 - 31 (20 bit)
access : read-write

LPL : Link Pointer Low (LPL)\nThese bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).
bits : 5 - 31 (27 bit)
access : read-write

ASSTMR : Asynchronous Schedule Sleep Timer This field defines the AsyncSchedSleepTime of EHCI spec. The asynchronous schedule sleep timer is used to control how often the host controller fetches asynchronous schedule list from system memory while the asynchronous schedule is empty. The default value of this timer is 12'hBD6. Because this timer is implemented in UTMI clock (30 MHz) domain, the default sleeping time will be about 100us.
bits : 0 - 11 (12 bit)
access : read-write

N_PORTS : Number of Physical Downstream Ports\nThis field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space (see Table 2-8). Valid values are in the range of 1H to FH.\nA zero in this field is undefined.
bits : 0 - 3 (4 bit)
access : read-only

PPC : Port Power Control\nThis field indicates whether the host controller implementation includes port power control. A one in this bit indicates the ports have port power switches. A zero in this bit indicates the port do not have port power stitches. The value of this field affects the functionality of the Port Power field in each port status and control register.
bits : 4 - 4 (1 bit)
access : read-only

N_PCC : Number of Ports Per Companion Controller\nThis field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software.\nFor example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first 4 are routed to companion controller 1 and the last two are routed to companion controller 2.\nThe number in this field must be consistent with N_PORTS and N_CC.
bits : 8 - 11 (4 bit)
access : read-only

N_CC : Number of Companion Controller\nThis field indicates the number of companion controllers associated with this USB 2.0 host controller.\nA zero in this field indicates there are no companion host controllers. Port-ownership hand-off is not supported. Only high-speed devices are supported on the host controller root ports.\nA value larger than zero in this field indicates there are companion USB 1.1 host controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed devices are supported on the host controller root ports.
bits : 12 - 15 (4 bit)
access : read-only

CF : Configure Flag (CF)\nHost software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CCS : Current Connect Status (Ready Only)\nThis value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set.\nThis field is zero if Port Power is zero.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CSC : Connect Status Change (R/W)\nIndicates a change has occurred in the port's Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set).Software sets this bit to 0 by writing a 1 to it.\nThis field is zero if Port Power is zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PE : Port Enabled/Disabled (R/W)\nPorts can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high-speed device.\nPorts can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.\nWhen the port is disabled (0b) downstream propagation of data is blocked on this port, except for reset.\nThis field is zero if Port Power is zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PEC : Port Enable/Disable Change (R/WC)\nFor the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it.\nThis field is zero if Port Power is zero.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

OCA : Over-current Active (Read Only)\nThis bit will automatically transition from a one to a zero when the over current condition is removed.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

OCC : Over-current Change (R/WC)
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FPR : Force Port Resume (R/W)\nThis functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspended (Suspend and Enabled bits are a one) and software transitions this bit to a one, then the effects on the bus are undefined.\nSoftware sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.\nNote that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return to high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to the high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.\nThis field is zero if Port Power is zero.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPEND : Suspend (R/W)\nPort Enabled Bit and Suspend bit of this register define the port states as follows:
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PRST : Port Reset (R/W) When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: when software writes this bit to a one, it must also write a zero to the Port Enable bit. Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2ms of software writing this bit to a zero. The HCHalted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HCHalted bit is a one. This field is zero if Port Power is zero.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSTS : Line Status (Read Only)\nThese bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is zero and the current connect status bit is set to a one.\nThe encoding of the bits are:\nBits[11:10] USB State Interpretation\nThis value of this field is undefined if Port Power is zero.
bits : 10 - 11 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PP : Port Power (PP)\nWhen an over-current condition is detected on a powered port and PPC is a one, the PP bit in each affected port may be transitioned by the host controller from a 1 to 0 (removing power from the port).
bits : 12 - 12 (1 bit)
access : read-write

PO : Port Owner (R/W)\nThis bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0 to 1 transition. This bit unconditionally goes to 1 whenever the Configured bit is zero.\nSystem software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port.
bits : 13 - 13 (1 bit)
access : read-write

PTC : Port Test Control (R/W)\nWhen this field is zero, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. The encoding of the test mode bits are (0x6 ~ 0xF are reserved):\n Bits Test Mode
bits : 16 - 19 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AC64 : 64-bit Addressing Capability
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PFLF : Programmable Frame List Flag
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ASPC : Asynchronous Schedule Park Capability
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

IST : Isochronous Scheduling Threshold\nThis field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule.\nWhen bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures (one or more) before flushing the state.
bits : 4 - 7 (4 bit)
access : read-only

EECP : EHCI Extended Capabilities Pointer (EECP)
bits : 8 - 15 (8 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SUSPEND : Suspend Assertion\nThis bit controls the suspend mode of USB PHY 0.\nWhile PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.\nThis bit is 1'b0 in default. This means the USB PHY 0 is suspended in default. It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKVALID : UTMI Clock Valid\nThis bit is a flag to indicate if the UTMI clock from USB 2.0 PHY is ready. S/W program must prevent to write other control registers before this UTMI clock valid flag is active.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SUSPEND : Suspend Assertion\nThis bit controls the suspend mode of USB PHY 1.\nWhile PHY was suspended, all circuits of PHY were powered down and outputs are tri-state.\nThis bit is 1'b0 in default. This means the USB PHY 0 is suspended in default. It is necessary to set this bit 1'b1 to make USB PHY 0 leave suspend mode before doing configuration of USB host.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.