Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
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CRYPTO_AES_DATOUT (AES_DATOUT)
CRYPTO_AES0_SADDR (AES0_SADDR)
CRYPTO_AES0_DADDR (AES0_DADDR)
CRYPTO_AES1_SADDR (AES1_SADDR)
CRYPTO_AES1_DADDR (AES1_DADDR)
CRYPTO_AES2_SADDR (AES2_SADDR)
CRYPTO_AES2_DADDR (AES2_DADDR)
CRYPTO_AES3_SADDR (AES3_SADDR)
CRYPTO_AES3_DADDR (AES3_DADDR)
CRYPTO_TDES0_KEY1H (TDES0_KEY1H)
CRYPTO_TDES0_KEY1L (TDES0_KEY1L)
CRYPTO_TDES0_KEY2H (TDES0_KEY2H)
CRYPTO_TDES0_KEY2L (TDES0_KEY2L)
CRYPTO_TDES0_KEY3H (TDES0_KEY3H)
CRYPTO_TDES0_KEY3L (TDES0_KEY3L)
CRYPTO_TDES0_SADDR (TDES0_SADDR)
CRYPTO_TDES0_DADDR (TDES0_DADDR)
CRYPTO_TDES_DATIN (TDES_DATIN)
CRYPTO_TDES_DATOUT (TDES_DATOUT)
CRYPTO_TDES1_KEY1H (TDES1_KEY1H)
CRYPTO_TDES1_KEY1L (TDES1_KEY1L)
CRYPTO_TDES1_KEY2H (TDES1_KEY2H)
CRYPTO_TDES1_KEY2L (TDES1_KEY2L)
CRYPTO_TDES1_KEY3H (TDES1_KEY3H)
CRYPTO_TDES1_KEY3L (TDES1_KEY3L)
CRYPTO_TDES1_SADDR (TDES1_SADDR)
CRYPTO_TDES1_DADDR (TDES1_DADDR)
CRYPTO_TDES2_KEY1H (TDES2_KEY1H)
CRYPTO_TDES2_KEY1L (TDES2_KEY1L)
CRYPTO_TDES2_KEY2H (TDES2_KEY2H)
CRYPTO_TDES2_KEY2L (TDES2_KEY2L)
CRYPTO_TDES2_KEY3H (TDES2_KEY3H)
CRYPTO_TDES2_KEY3L (TDES2_KEY3L)
CRYPTO_TDES2_SADDR (TDES2_SADDR)
CRYPTO_TDES2_DADDR (TDES2_DADDR)
CRYPTO_TDES3_KEY1H (TDES3_KEY1H)
CRYPTO_TDES3_KEY1L (TDES3_KEY1L)
CRYPTO_TDES3_KEY2H (TDES3_KEY2H)
CRYPTO_TDES3_KEY2L (TDES3_KEY2L)
CRYPTO_TDES3_KEY3H (TDES3_KEY3H)
CRYPTO_TDES3_KEY3L (TDES3_KEY3L)
CRYPTO_TDES3_SADDR (TDES3_SADDR)
CRYPTO_TDES3_DADDR (TDES3_DADDR)
CRYPTO_HMAC_DGST0 (HMAC_DGST0)
CRYPTO_HMAC_DGST1 (HMAC_DGST1)
CRYPTO_HMAC_DGST2 (HMAC_DGST2)
CRYPTO_HMAC_DGST3 (HMAC_DGST3)
CRYPTO_HMAC_DGST4 (HMAC_DGST4)
CRYPTO_HMAC_DGST5 (HMAC_DGST5)
CRYPTO_HMAC_DGST6 (HMAC_DGST6)
CRYPTO_HMAC_DGST7 (HMAC_DGST7)
CRYPTO_HMAC_DGST8 (HMAC_DGST8)
CRYPTO_HMAC_DGST9 (HMAC_DGST9)
CRYPTO_HMAC_DGST10 (HMAC_DGST10)
CRYPTO_HMAC_DGST11 (HMAC_DGST11)
CRYPTO_HMAC_DGST12 (HMAC_DGST12)
CRYPTO_HMAC_DGST13 (HMAC_DGST13)
CRYPTO_HMAC_DGST14 (HMAC_DGST14)
CRYPTO_HMAC_DGST15 (HMAC_DGST15)
CRYPTO_HMAC_KEYCNT (HMAC_KEYCNT)
CRYPTO_HMAC_SADDR (HMAC_SADDR)
CRYPTO_HMAC_DMACNT (HMAC_DMACNT)
CRYPTO_HMAC_DATIN (HMAC_DATIN)
CRYPTO_AES_FDBCK0 (AES_FDBCK0)
CRYPTO_AES_FDBCK1 (AES_FDBCK1)
CRYPTO_AES_FDBCK2 (AES_FDBCK2)
CRYPTO_AES_FDBCK3 (AES_FDBCK3)
CRYPTO_TDES_FDBCKH (TDES_FDBCKH)
CRYPTO_TDES_FDBCKL (TDES_FDBCKL)
CRYPTO_ECC_STARTREG (ECC_STARTREG)
CRYPTO_ECC_WORDCNT (ECC_WORDCNT)
Crypto Interrupt Enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIEN : AES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES interrupt Disabled
#1 : 1
AES interrupt Enabled
End of enumeration elements list.
AESEIEN : AES Error Flag Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES error interrupt flag Disabled
#1 : 1
AES error interrupt flag Enabled
End of enumeration elements list.
TDESIEN : TDES/DES Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES/DES interrupt Disabled
#1 : 1
TDES/DES interrupt Enabled
End of enumeration elements list.
TDESEIEN : TDES/DES Error Flag Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES/DES error interrupt flag Disabled
#1 : 1
TDES/DES error interrupt flag Enabled
End of enumeration elements list.
PRNGIEN : PRNG Interrupt Enable Bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PRNG interrupt Disabled
#1 : 1
PRNG interrupt Enabled
End of enumeration elements list.
ECCIEN : ECC Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC interrupt Disabled
#1 : 1
ECC interrupt Enabled
End of enumeration elements list.
ECCEIEN : ECC Error Interrupt Enable Bit
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC error interrupt flag Disabled
#1 : 1
ECC error interrupt flag Enabled
End of enumeration elements list.
HMACIEN : SHA/HMAC Interrupt Enable Bit\nNote: In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine. In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA/HMAC interrupt Disabled
#1 : 1
SHA/HMAC interrupt Enabled
End of enumeration elements list.
HMACEIEN : SHA/HMAC Error Interrupt Enable Bit
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA/HMAC error interrupt flag Disabled
#1 : 1
SHA/HMAC error interrupt flag Enabled
End of enumeration elements list.
PRNG Generated Key0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
KEY : Store PRNG Generated Key (Read Only)\nThe bits store the key that is generated by PRNG.
bits : 0 - 31 (32 bit)
access : read-only
AES Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : AES Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start AES engine. BUSY flag will be set
End of enumeration elements list.
STOP : AES Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop AES engine
End of enumeration elements list.
KEYSZ : AES Key Size\nThis bit defines three different key size for AES operation.\nIf the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
bits : 2 - 3 (2 bit)
access : read-write
DMALAST : AES Last Block\nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.\nThis bit is always 0 when it's read back. Must be written again once START is triggered.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : AES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : AES Engine DMA Enable Bit\nThe AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES DMA engine Disabled
#1 : 1
AES_DMA engine Enabled
End of enumeration elements list.
OPMODE : AES Engine Operation Modes
bits : 8 - 15 (8 bit)
access : read-write
Enumeration:
0x00 : 0
ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode)
0x02 : 2
CFB (Cipher Feedback Mode)
0x03 : 3
OFB (Output Feedback Mode)
0x04 : 4
CTR (Counter Mode)
0x10 : 16
CBC-CS1 (CBC Ciphertext-Stealing 1 Mode)
0x11 : 17
CBC-CS2 (CBC Ciphertext-Stealing 2 Mode)
0x12 : 18
CBC-CS3 (CBC Ciphertext-Stealing 3 Mode)
End of enumeration elements list.
ENCRYPTO : AES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
AES engine executes decryption operation
#1 : 1
AES engine executes encryption operation
End of enumeration elements list.
OUTSWAP : AES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : AES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
CHANNEL : AES Engine Working Channel
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Current control register setting is for channel 0
#01 : 1
Current control register setting is for channel 1
#10 : 2
Current control register setting is for channel 2
#11 : 3
Current control register setting is for channel 3
End of enumeration elements list.
KEYUNPRT : Unprotect Key\nWriting 0 to CRYPTO_AES_CTL[31] and '10110' to CRYPTO_AES_CTL[30:26] is to unprotect the AES key.\nThe KEYUNPRT can be read and written. When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write
KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Protect the content of the AES key from reading. The return value for reading CRYPTO_AESn_KEYx is not the content of the registers CRYPTO_AESn_KEYx. Once it is set, it can be cleared by asserting KEYUNPRT. And the key content would be cleared as well
End of enumeration elements list.
AES Engine Flag
address_offset : 0x104 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : AES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The AES engine is idle or finished
#1 : 1
The AES engine is under processing
End of enumeration elements list.
INBUFEMPTY : AES Input Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
There are some data in input buffer waiting for the AES engine to process
#1 : 1
AES input buffer is empty. Software needs to feed data to the AES engine. Otherwise, the AES engine will be pending to wait for input data
End of enumeration elements list.
INBUFFULL : AES Input Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES input buffer is not full. Software can feed the data into the AES engine
#1 : 1
AES input buffer is full. Software cannot feed data to the AES engine. Otherwise, the flag INBUFERR will be set to 1
End of enumeration elements list.
INBUFERR : AES Input Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during feeding data to the AES engine
End of enumeration elements list.
CNTERR : CRYPTO_AESn_CNT Setting Error
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error in CRYPTO_AESn_CNT setting
#1 : 1
CRYPTO_AESn_CNT is 0 or not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode if DMAEN (CRYPTO_AES_CTL[7]) is enabled
End of enumeration elements list.
OUTBUFEMPTY : AES Out Buffer Empty
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES output buffer is not empty. There are some valid data kept in output buffer
#1 : 1
AES output buffer is empty. Software cannot get data from CRYPTO_AES_DATOUT. Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty
End of enumeration elements list.
OUTBUFFULL : AES Out Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
AES output buffer is not full
#1 : 1
AES output buffer is full, and software needs to get data from CRYPTO_AES_DATOUT. Otherwise, the AES engine will be pending since the output buffer is full
End of enumeration elements list.
OUTBUFERR : AES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during getting the result from AES engine
End of enumeration elements list.
BUSERR : AES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and AES engine
End of enumeration elements list.
AES Engine Data Input Port Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : AES Engine Input Port\nCPU feeds data to AES engine through this port by checking CRYPTO_AES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write
AES Engine Data Output Port Register
address_offset : 0x10C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : AES Engine Output Port\nCPU gets results from the AES engine through this port by checking CRYPTO_AES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only
AES Key Word 0 Register for Channel 0
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : CRYPTO_AESn_KEYx\nThe KEY keeps the security key for AES operation.\nThe security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key. {CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 128-bit security key for AES operation. {CRYPTO_AESn_KEY5, CRYPTO_AESn_KEY4, CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 192-bit security key for AES operation. {CRYPTO_AESn_KEY7, CRYPTO_AESn_KEY6, CRYPTO_AESn_KEY5, CRYPTO_AESn_KEY4, CRYPTO_AESn_KEY3, CRYPTO_AESn_KEY2, CRYPTO_AESn_KEY1, CRYPTO_AESn_KEY0} stores the 256-bit security key for AES operation.
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word 1 Register for Channel 0
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 0
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 0
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 0
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 0
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 0
address_offset : 0x128 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 0
address_offset : 0x12C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 0
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV : AES Initial Vectors\nFour initial vectors (CRYPTO_AESn_IV0, CRYPTO_AESn_IV1, CRYPTO_AESn_IV2, and CRYPTO_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode. Four registers (CRYPTO_AESn_IV0, CRYPTO_AESn_IV1, CRYPTO_AESn_IV2, and CRYPTO_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write
AES Initial Vector Word 1 Register for Channel 0
address_offset : 0x134 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 0
address_offset : 0x138 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 0
address_offset : 0x13C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 0
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : AES DMA Source Address\nThe AES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the AES accelerator can read the plain text (encryption) / cipher text (descryption) from SRAM memory space and do AES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of SADDR are ignored.\nSADDR can be read and written. Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AESn_SADDR before triggering START.\nThe value of CRYPTO_AESn_SADDR and CRYPTO_AESn_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write
AES DMA Destination Address Register for Channel 0
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : AES DMA Destination Address\nThe AES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the AES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the AES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of DADDR are ignored.\nDADDR can be read and written. Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation. But the value of DADDR will be updated later on. Consequently, software can prepare the destination address for the next AES operation.\nIn DMA mode, software can update the next CRYPTO_AESn_DADDR before triggering START. \nThe value of CRYPTO_AESn_SADDR and CRYPTO_AESn_DADDR can be the same.
bits : 0 - 31 (32 bit)
access : read-write
AES Byte Count Register for Channel 0
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : AES Byte Count\nThe CRYPTO_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode. The CRYPTO_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_AESn_CNT can be read and written. Writing to CRYPTO_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation. But the value of CRYPTO_AESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next AES operation.\nAccording to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be more than 16 bytes. Operations that are qual or less than one block will output unexpected result.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRYPTO_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
bits : 0 - 31 (32 bit)
access : read-write
AES Key Word 0 Register for Channel 1
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 1
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 1
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 1
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 1
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 1
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 1
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 1
address_offset : 0x168 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 1
address_offset : 0x16C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 1
address_offset : 0x170 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 1
address_offset : 0x174 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 1
address_offset : 0x178 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 1
address_offset : 0x17C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key2
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 1
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 1
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 2
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 2
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 2
address_offset : 0x190 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 2
address_offset : 0x194 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 2
address_offset : 0x198 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 2
address_offset : 0x19C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 2
address_offset : 0x1A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 2
address_offset : 0x1A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 2
address_offset : 0x1A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 2
address_offset : 0x1AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 2
address_offset : 0x1B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 2
address_offset : 0x1B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 2
address_offset : 0x1B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 2
address_offset : 0x1BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key3
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 2
address_offset : 0x1C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 0 Register for Channel 3
address_offset : 0x1C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 1 Register for Channel 3
address_offset : 0x1C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 2 Register for Channel 3
address_offset : 0x1CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 3 Register for Channel 3
address_offset : 0x1D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 4 Register for Channel 3
address_offset : 0x1D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 5 Register for Channel 3
address_offset : 0x1D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 6 Register for Channel 3
address_offset : 0x1DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Key Word 7 Register for Channel 3
address_offset : 0x1E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 0 Register for Channel 3
address_offset : 0x1E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 1 Register for Channel 3
address_offset : 0x1E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 2 Register for Channel 3
address_offset : 0x1EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Initial Vector Word 3 Register for Channel 3
address_offset : 0x1F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Source Address Register for Channel 3
address_offset : 0x1F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES DMA Destination Address Register for Channel 3
address_offset : 0x1F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Byte Count Register for Channel 3
address_offset : 0x1FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key4
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : TDES/DES Engine Start\nNote: The bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start TDES/DES engine. The flag BUSY would be set
End of enumeration elements list.
STOP : TDES/DES Engine Stop\nNote: The bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop TDES/DES engine
End of enumeration elements list.
TMODE : TDES/DES Engine Operating Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set DES mode for TDES/DES engine
#1 : 1
Set Triple DES mode for TDES/DES engine
End of enumeration elements list.
_3KEYS : TDES/DES Key Number
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Select KEY1 and KEY2 in TDES/DES engine
#1 : 1
Triple keys in TDES/DES engine Enabled
End of enumeration elements list.
DMALAST : TDES/DES Engine Start for the Last Block \nIn DMA mode, this bit must be set as beginning the last DMA cascade round.\nIn Non-DMA mode, this bit must be set as feeding in last block of data.
bits : 5 - 5 (1 bit)
access : read-write
DMACSCAD : TDES/DES Engine DMA with Cascade Mode
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
DMA cascade function Disabled
#1 : 1
In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation
End of enumeration elements list.
DMAEN : TDES/DES Engine DMA Enable Bit\nTDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES_DMA engine Disabled
#1 : 1
TDES_DMA engine Enabled
End of enumeration elements list.
OPMODE : TDES/DES Engine Operation Mode
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x00 : 0
ECB (Electronic Codebook Mode)
0x01 : 1
CBC (Cipher Block Chaining Mode)
0x02 : 2
CFB (Cipher Feedback Mode)
0x03 : 3
OFB (Output Feedback Mode)
0x04 : 4
CTR (Counter Mode)
End of enumeration elements list.
ENCRYPTO : TDES/DES Encryption/Decryption
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
TDES engine executes decryption operation
#1 : 1
TDES engine executes encryption operation
End of enumeration elements list.
BLKSWAP : TDES/DES Engine Block Double Word Endian Swap
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order, e.g. {WORD_H, WORD_L}
#1 : 1
When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}
End of enumeration elements list.
OUTSWAP : TDES/DES Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : TDES/DES Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
CHANNEL : TDES/DES Engine Working Channel
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Current control register setting is for channel 0
#01 : 1
Current control register setting is for channel 1
#10 : 2
Current control register setting is for channel 2
#11 : 3
Current control register setting is for channel 3
End of enumeration elements list.
KEYUNPRT : Unprotect Key\nWriting 0 to CRYPTO_TDES_CTL [31] and '10110' to CRYPTO_TDES_CTL [30:26] is to unprotect TDES key.\nThe KEYUNPRT can be read and written. When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
bits : 26 - 30 (5 bit)
access : read-write
KEYPRT : Protect Key\nRead as a flag to reflect KEYPRT.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
This bit is to protect the content of TDES key from reading. The return value for reading CRYPTO_ TDESn_KEYxH/L is not the content in the registers CRYPTO_ TDESn_KEYxH/L. Once it is set, it can be cleared by asserting KEYUNPRT. The key content would be cleared as well
End of enumeration elements list.
TDES/DES Engine Flag
address_offset : 0x204 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : TDES/DES Engine Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES engine is idle or finished
#1 : 1
TDES/DES engine is under processing
End of enumeration elements list.
INBUFEMPTY : TDES/DES in Buffer Empty
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
There are some data in input buffer waiting for the TDES/DES engine to process
#1 : 1
TDES/DES input buffer is empty. Software needs to feed data to the TDES/DES engine. Otherwise, the TDES/DES engine will be pending to wait for input data
End of enumeration elements list.
INBUFFULL : TDES/DES in Buffer Full Flag
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine
#1 : 1
TDES input buffer is full. Software cannot feed data to the TDES/DES engine. Otherwise, the flag INBUFERR will be set to 1
End of enumeration elements list.
INBUFERR : TDES/DES in Buffer Error Flag
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during feeding data to the TDES/DES engine
End of enumeration elements list.
OUTBUFEMPTY : TDES/DES Output Buffer Empty Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES output buffer is not empty. There are some valid data kept in output buffer
#1 : 1
TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT. Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty
End of enumeration elements list.
OUTBUFFULL : TDES/DES Output Buffer Full Flag
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
TDES/DES output buffer is not full
#1 : 1
TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT. Otherwise, the TDES/DES engine will be pending since output buffer is full
End of enumeration elements list.
OUTBUFERR : TDES/DES Out Buffer Error Flag
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Error happens during getting test result from TDES/DES engine
End of enumeration elements list.
BUSERR : TDES/DES DMA Access Bus Error Flag
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and TDES/DES engine
End of enumeration elements list.
TDES/DES Key 1 High Word Register for Channel 0
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : TDES/DES Key High/Low Word\nThe key registers for TDES/DES algorithm calculation\nThe security key for the TDES/DES accelerator is 64 bits. Thus, it needs two 32-bit registers to store a security key. The register CRYPTO_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRYPTO_TDESn_KEYxL is used to keep the bit [31:0].
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Key 1 Low Word Register for Channel 0
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 0
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 0
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 0
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 0
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 0
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IV : TDES/DES Initial Vector High/Low Word\nInitial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode. IV is Nonce counter for TDES/DES engine in CTR mode.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Initial Vector Low Word Register for Channel 0
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 0
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : TDES/DES DMA Source Address\nThe TDES/DES accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_TDESn_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the TDES/DES accelerator can read the plain text (encryption) / cipher text (decryption) from SRAM memory space and do TDES/DES operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_TDESn_SADDR are ignored.\nCRYPTO_TDESn_SADDR can be read and written. Writing to CRYPTO_TDESn_SADDR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRYPTO_TDESn_SADDR before triggering START.\nCRYPTO_TDESn_SADDR and CRYPTO_TDESn_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES DMA Destination Address Register for Channel 0
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : TDES/DES DMA Destination Address\nThe TDES/DES accelerator supports DMA function to transfer the cipher text between SRAM memory space and embedded FIFO. The CRYPTO_TDESn_DADDR keeps the destination address of the data buffer where the engine output's text will be stored. Based on the destination address, the TDES/DES accelerator can write the cipher text (encryption) / plain text (decryption) back to SRAM memory space after the TDES/DES operation is finished. The start of destination address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_TDESn_DADDR are ignored.\nCRYPTO_TDESn_DADDR can be read and written. Writing to CRYPTO_TDESn_DADDR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_DADDR will be updated later on. Consequently, software can prepare the destination address for the next TDES/DES operation.\nIn DMA mode, software can update the next CRYPTO_TDESn_DADDR before triggering START. \nCRYPTO_TDESn_SADDR and CRYPTO_TDESn_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Byte Count Register for Channel 0
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : TDES/DES Byte Count \nThe CRYPTO_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode. The CRYPTO_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_TDESn_CNT can be read and written. Writing to CRYPTO_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation. But the value of CRYPTO_TDESn_CNT will be updated later on. Consequently, software can prepare the byte count of data for the next TDES /DES operation.\nIn Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRYPTO_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Engine Input Data Word Register
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : TDES/DES Engine Input Port\nCPU feeds data to TDES/DES engine through this port by checking CRYPTO_TDES_STS. Feed data as INBUFFULL is 0.
bits : 0 - 31 (32 bit)
access : read-write
TDES/DES Engine Output Data Word Register
address_offset : 0x238 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATOUT : TDES/DES Engine Output Port\nCPU gets result from the TDES/DES engine through this port by checking CRYPTO_TDES_STS. Get data as OUTBUFEMPTY is 0.
bits : 0 - 31 (32 bit)
access : read-only
PRNG Generated Key5
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 1
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 1
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 1
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 1
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 1
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 1
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 1
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 1
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 1
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 1
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 1
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key6
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 2
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 2
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 2
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 2
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 2
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 2
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 2
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 2
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 2
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 2
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 2
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Generated Key7
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 High Word Register for Channel 3
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Key 1 Low Word Register for Channel 3
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 High Word Register for Channel 3
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 2 Low Word Register for Channel 3
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 High Word Register for Channel 3
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES Key 3 Low Word Register for Channel 3
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector High Word Register for Channel 3
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Initial Vector Low Word Register for Channel 3
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Source Address Register for Channel 3
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES DMA Destination Address Register for Channel 3
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Byte Count Register for Channel 3
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : SHA/HMAC Engine Start\nNote: This bit is always 0 when it's read back.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start SHA/HMAC engine. BUSY flag will be set
End of enumeration elements list.
STOP : SHA/HMAC Engine Stop\nNote: This bit is always 0 when it's read back.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Stop SHA/HMAC engine
End of enumeration elements list.
HMACEN : HMAC_SHA Engine Operating Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Execute SHA function
#1 : 1
Execute HMAC function
End of enumeration elements list.
DMALAST : SHA/HMAC Last Block\nThis bit must be set as feeding in last byte of data.
bits : 5 - 5 (1 bit)
access : read-write
DMAEN : SHA/HMAC Engine DMA Enable Bit\nSHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
SHA/HMAC DMA engine Disabled
#1 : 1
SHA/HMAC DMA engine Enabled
End of enumeration elements list.
OPMODE : SHA/HMAC Engine Operation Modes\n0x0xx: SHA160\n0x100: SHA256\n0x101: SHA224\n0x110: SHA512\n0x111: SHA384
bits : 8 - 10 (3 bit)
access : read-write
OUTSWAP : SHA/HMAC Engine Output Data Swap
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
INSWAP : SHA/HMAC Engine Input Data Swap
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Keep the original order
#1 : 1
The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}
End of enumeration elements list.
SHA/HMAC Status Flag
address_offset : 0x304 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : SHA/HMAC Engine Busy
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
SHA/HMAC engine is idle or finished
#1 : 1
SHA/HMAC engine is busy
End of enumeration elements list.
DMABUSY : SHA/HMAC Engine DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
SHA/HMAC DMA engine is idle or finished
#1 : 1
SHA/HMAC DMA engine is busy
End of enumeration elements list.
DMAERR : SHA/HMAC Engine DMA Error Flag
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Show the SHA/HMAC engine access normal
#1 : 1
Show the SHA/HMAC engine access error
End of enumeration elements list.
DATINREQ : SHA/HMAC Non-dMA Mode Data Input Request
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No effect
#1 : 1
Request SHA/HMAC Non-DMA mode data input
End of enumeration elements list.
SHA/HMAC Digest Message 0
address_offset : 0x308 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DGST : SHA/HMAC Digest Message Output Register\nFor SHA-160, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST4.\nFor SHA-224, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST6.\nFor SHA-256, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST7.\nFor SHA-384, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST11.\nFor SHA-512, the digest is stored in CRYPTO_HMAC_DGST0 ~ CRYPTO_HMAC_DGST15.
bits : 0 - 31 (32 bit)
access : read-only
SHA/HMAC Digest Message 1
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 2
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 3
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 4
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 5
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 6
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 7
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 8
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 9
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 10
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 11
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 12
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 13
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 14
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Digest Message 15
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SHA/HMAC Key Byte Count Register
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEYCNT : SHA/HMAC Key Byte Count\nThe CRYPTO_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates. The register is 32-bit and the maximum byte count is 4G bytes. It can be read and written. \nWriting to the register CRYPTO_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation. But the value of CRYPTO_SHA _KEYCNT will be updated later on. Consequently, software can prepare the key count for the next SHA/HMAC operation.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC DMA Source Address Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADDR : SHA/HMAC DMA Source Address\nThe SHA/HMAC accelerator supports DMA function to transfer the plain text between SRAM memory space and embedded FIFO. The CRYPTO_HMAC_SADDR keeps the source address of the data buffer where the source text is stored. Based on the source address, the SHA/HMAC accelerator can read the plain text from SRAM memory space and do SHA/HMAC operation. The start of source address should be located at word boundary. In other words, bit 1 and 0 of CRYPTO_HMAC_SADDR are ignored.\nCRYPTO_HMAC_SADDR can be read and written. Writing to CRYPTO_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation. But the value of CRYPTO_HMAC_SADDR will be updated later on. Consequently, software can prepare the DMA source address for the next SHA/HMAC operation.\nIn DMA mode, software can update the next CRYPTO_HMAC_SADDR before triggering START.\nCRYPTO_HMAC_SADDR and CRYPTO_HMAC_DADDR can be the same in the value.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC Byte Count Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMACNT : SHA/HMAC Operation Byte Count\nThe CRYPTO_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode. The CRYPTO_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes.\nCRYPTO_HMAC_DMACNT can be read and written. Writing to CRYPTO_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation. But the value of CRYPTO_HMAC_DMACNT will be updated later on. Consequently, software can prepare the byte count of data for the next SHA/HMAC operation.\nIn Non-DMA mode, CRYPTO_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
bits : 0 - 31 (32 bit)
access : read-write
SHA/HMAC Engine Non-dMA Mode Data Input Port Register
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATIN : SHA/HMAC Engine Input Port\nCPU feeds data to SHA/HMAC engine through this port by checking CRYPTO_HMAC_STS. Feed data as DATINREQ is 1.
bits : 0 - 31 (32 bit)
access : read-write
Crypto Interrupt Flag
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AESIF : AES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES interrupt
#1 : 1
AES encryption/decryption done interrupt
End of enumeration elements list.
AESEIF : AES Error Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No AES error
#1 : 1
AES encryption/decryption error interrupt
End of enumeration elements list.
TDESIF : TDES/DES Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TDES/DES interrupt
#1 : 1
TDES/DES encryption/decryption done interrupt
End of enumeration elements list.
TDESEIF : TDES/DES Error Flag\nThis bit includes the operating and setting error. The detailed flag is shown in the CRYPTO_TDES_STS register. This includes operating and setting error.\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No TDES/DES error
#1 : 1
TDES/DES encryption/decryption error interrupt
End of enumeration elements list.
PRNGIF : PRNG Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No PRNG interrupt
#1 : 1
PRNG key generation done interrupt
End of enumeration elements list.
ECCIF : ECC Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ECC interrupt
#1 : 1
ECC operation done interrupt
End of enumeration elements list.
ECCEIF : ECC Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_ECC_STS register.\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ECC error
#1 : 1
ECC error interrupt
End of enumeration elements list.
HMACIF : SHA/HMAC Finish Interrupt Flag\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA/HMAC interrupt
#1 : 1
SHA/HMAC operation done interrupt
End of enumeration elements list.
HMACEIF : SHA/HMAC Error Flag\nThis register includes operating and setting error. The detail flag is shown in CRYPTO_HMAC_STS register.\nThis bit is cleared by writing 1, and it has no effect by writing 0.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No SHA/HMAC error
#1 : 1
SHA/HMAC error interrupt
End of enumeration elements list.
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x50 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : AES Feedback Information\nThe feedback value is 128 bits in size.\nThe AES engine uses the data from CRYPTO_AES_FDBCKx as the data inputted to CRYPTO_AESn_IVx for the next block in DMA cascade mode.\nThe AES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_AESn_IVx in the same channel operation, and then continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AES Engine Output Feedback Data After Cryptographic Operation
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDES/DES Engine Output Feedback High Word Data After Cryptographic Operation
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FDBCK : TDES/DES Feedback\nThe feedback value is 64 bits in size.\nThe TDES/DES engine uses the data from {CRYPTO_TDES_FDBCKH, CRYPTO_TDES_FDBCKL} as the data inputted to {CRYPTO_TDESn_IVH, CRYPTO_TDESn_IVL} for the next block in DMA cascade mode. The feedback register is for CBC, CFB, and OFB mode.\nTDES/DES engine outputs feedback information for IV in the next block's operation. Software can use this feedback information to implement more than four DMA channels. Software can store that feedback value temporarily. After switching back, fill the stored feedback value to CRYPTO_TDESn_IVH/L in the same channel operation. Then can continue the operation with the original setting.
bits : 0 - 31 (32 bit)
access : read-only
TDES/DES Engine Output Feedback Low Word Data After Cryptographic Operation
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRNG Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : Start PRNG Engine
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop PRNG engine
#1 : 1
Generate new key and store the new key to register CRYPTO_PRNG_KEYx, which will be cleared when the new key is generated
End of enumeration elements list.
SEEDRLD : Reload New Seed for PRNG Engine
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Generating key based on the current seed
#1 : 1
Reload new seed
End of enumeration elements list.
KEYSZ : PRNG Generate Key Size
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
64 bits
#01 : 1
128 bits
#10 : 2
192 bits
#11 : 3
256 bits
End of enumeration elements list.
BUSY : PRNG Busy (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
PRNG engine is idle
#1 : 1
Indicate that the PRNG engine is generating CRYPTO_PRNG_KEYx
End of enumeration elements list.
ECC Control Register
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
START : ECC Accelerator Start\nThis bit is always 0 when it's read back.\nECC accelerator will ignore this START signal when BUSY flag is 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Start ECC accelerator. BUSY flag will be set
End of enumeration elements list.
STOP : ECC Accelerator Stop\nThis bit is always 0 when it's read back.\nRemember to clear ECC interrupt flag after stopping ECC accelerator.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Abort ECC accelerator and make it into idle state
End of enumeration elements list.
DMAEN : ECC Accelerator DMA Enable Bit\nOnly when START and DMAEN are 1, ECC DMA engine will be active
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
ECC DMA engine Disabled
#1 : 1
ECC DMA engine Enabled
End of enumeration elements list.
FSEL : Field Selection
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Binary Field (GF(2m ))
#1 : 1
Prime Field (GF(p))
End of enumeration elements list.
ECCOP : Point Operation for BF and PF\nBesides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11.
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
#00 : 0
Point multiplication :
#01 : 1
Modulus operation : choose by MODOP (CRYPTO_ECC_CTL[12:11])
#10 : 2
Point addition :
#11 : 3
Point doubling :
End of enumeration elements list.
MODOP : Modulus Operation for PF
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
#00 : 0
Division :
#01 : 1
Multiplication :
#10 : 2
Addition :
#11 : 3
Subtraction :
End of enumeration elements list.
LDP1 : The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1)
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The register for POINTX1 and POINTY1 is not modified by DMA or user
#1 : 1
The register for POINTX1 and POINTY1 is modified by DMA or user
End of enumeration elements list.
LDP2 : The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2)
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
The register for POINTX2 and POINTY2 is not modified by DMA or user
#1 : 1
The register for POINTX2 and POINTY2 is modified by DMA or user
End of enumeration elements list.
LDA : The Control Signal of Register for the Parameter CURVEA of Elliptic Curve
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
The register for CURVEA is not modified by DMA or user
#1 : 1
The register for CURVEA is modified by DMA or user
End of enumeration elements list.
LDB : The Control Signal of Register for the Parameter CURVEB of Elliptic Curve
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
The register for CURVEB is not modified by DMA or user
#1 : 1
The register for CURVEB is modified by DMA or user
End of enumeration elements list.
LDN : The Control Signal of Register for the Parameter CURVEN of Elliptic Curve
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
The register for CURVEN is not modified by DMA or user
#1 : 1
The register for CURVEN is modified by DMA or user
End of enumeration elements list.
LDK : The Control Signal of Register for SCALARK
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
The register for SCALARK is not modified by DMA or user
#1 : 1
The register for SCALARK is modified by DMA or user
End of enumeration elements list.
CURVEM : The key length of elliptic curve.
bits : 22 - 31 (10 bit)
access : read-write
ECC Status Register
address_offset : 0x804 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : ECC Accelerator Busy Flag\nRemember to clear ECC interrupt flag after ECC accelerator finished
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
The ECC accelerator is idle or finished
#1 : 1
The ECC accelerator is under processing and protects all registers
End of enumeration elements list.
DMABUSY : ECC DMA Busy Flag
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
ECC DMA is idle or finished
#1 : 1
ECC DMA is busy
End of enumeration elements list.
BUSERR : ECC DMA Access Bus Error Flag
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
No error
#1 : 1
Bus error will stop DMA operation and ECC accelerator
End of enumeration elements list.
ECC the X-coordinate Word0 of the First Point
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POINTX1 : ECC the x-coordinate Value of the First Point (POINTX1)\nFor B-163 or K-163, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor B-233 or K-233, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor B-283 or K-283, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_08\nFor B-409 or K-409, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_12\nFor B-571 or K-571, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_17\nFor P-192, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_05\nFor P-224, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_06\nFor P-256, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_07\nFor P-384, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_11\nFor P-521, POINTX1 is stored in CRYPTO_ECC_X1_00~CRYPTO_ECC_X1_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the X-coordinate Word1 of the First Point
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word2 of the First Point
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word3 of the First Point
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word4 of the First Point
address_offset : 0x818 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word5 of the First Point
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word6 of the First Point
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word7 of the First Point
address_offset : 0x824 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word8 of the First Point
address_offset : 0x828 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word9 of the First Point
address_offset : 0x82C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word10 of the First Point
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word11 of the First Point
address_offset : 0x834 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word12 of the First Point
address_offset : 0x838 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word13 of the First Point
address_offset : 0x83C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word14 of the First Point
address_offset : 0x840 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word15 of the First Point
address_offset : 0x844 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word16 of the First Point
address_offset : 0x848 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word17 of the First Point
address_offset : 0x84C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word0 of the First Point
address_offset : 0x850 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POINTY1 : ECC the Y-coordinate Value of the First Point (POINTY1)\nFor B-163 or K-163, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor B-233 or K-233, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor B-283 or K-283, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_08\nFor B-409 or K-409, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_12\nFor B-571 or K-571, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_17\nFor P-192, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_05\nFor P-224, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_06\nFor P-256, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_07\nFor P-384, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_11\nFor P-521, POINTY1 is stored in CRYPTO_ECC_Y1_00~CRYPTO_ECC_Y1_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the Y-coordinate Word1 of the First Point
address_offset : 0x854 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word2 of the First Point
address_offset : 0x858 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word3 of the First Point
address_offset : 0x85C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word4 of the First Point
address_offset : 0x860 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word5 of the First Point
address_offset : 0x864 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word6 of the First Point
address_offset : 0x868 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word7 of the First Point
address_offset : 0x86C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word8 of the First Point
address_offset : 0x870 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word9 of the First Point
address_offset : 0x874 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word10 of the First Point
address_offset : 0x878 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word11 of the First Point
address_offset : 0x87C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word12 of the First Point
address_offset : 0x880 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word13 of the First Point
address_offset : 0x884 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word14 of the First Point
address_offset : 0x888 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word15 of the First Point
address_offset : 0x88C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word16 of the First Point
address_offset : 0x890 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word17 of the First Point
address_offset : 0x894 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word0 of the Second Point
address_offset : 0x898 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POINTX2 : ECC the x-coordinate Value of the Second Point (POINTX2)\nFor B-163 or K-163, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor B-233 or K-233, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor B-283 or K-283, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_08\nFor B-409 or K-409, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_12\nFor B-571 or K-571, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_17\nFor P-192, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_05\nFor P-224, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_06\nFor P-256, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_07\nFor P-384, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_11\nFor P-521, POINTX2 is stored in CRYPTO_ECC_X2_00~CRYPTO_ECC_X2_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the X-coordinate Word1 of the Second Point
address_offset : 0x89C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word2 of the Second Point
address_offset : 0x8A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word3 of the Second Point
address_offset : 0x8A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word4 of the Second Point
address_offset : 0x8A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word5 of the Second Point
address_offset : 0x8AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word6 of the Second Point
address_offset : 0x8B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word7 of the Second Point
address_offset : 0x8B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word8 of the Second Point
address_offset : 0x8B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word9 of the Second Point
address_offset : 0x8BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word10 of the Second Point
address_offset : 0x8C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word11 of the Second Point
address_offset : 0x8C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word12 of the Second Point
address_offset : 0x8C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word13 of the Second Point
address_offset : 0x8CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word14 of the Second Point
address_offset : 0x8D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word15 of the Second Point
address_offset : 0x8D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word16 of the Second Point
address_offset : 0x8D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the X-coordinate Word17 of the Second Point
address_offset : 0x8DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word0 of the Second Point
address_offset : 0x8E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POINTY2 : ECC the Y-coordinate Value of the Second Point (POINTY2)\nFor B-163 or K-163, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor B-233 or K-233, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor B-283 or K-283, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_08\nFor B-409 or K-409, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_12\nFor B-571 or K-571, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_17\nFor P-192, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_05\nFor P-224, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_06\nFor P-256, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_07\nFor P-384, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_11\nFor P-521, POINTY2 is stored in CRYPTO_ECC_Y2_00~CRYPTO_ECC_Y2_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the Y-coordinate Word1 of the Second Point
address_offset : 0x8E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word2 of the Second Point
address_offset : 0x8E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word3 of the Second Point
address_offset : 0x8EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word4 of the Second Point
address_offset : 0x8F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word5 of the Second Point
address_offset : 0x8F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word6 of the Second Point
address_offset : 0x8F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word7 of the Second Point
address_offset : 0x8FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word8 of the Second Point
address_offset : 0x900 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word9 of the Second Point
address_offset : 0x904 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word10 of the Second Point
address_offset : 0x908 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word11 of the Second Point
address_offset : 0x90C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word12 of the Second Point
address_offset : 0x910 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word13 of the Second Point
address_offset : 0x914 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word14 of the Second Point
address_offset : 0x918 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word15 of the Second Point
address_offset : 0x91C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word16 of the Second Point
address_offset : 0x920 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Y-coordinate Word17 of the Second Point
address_offset : 0x924 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word0 of Elliptic Curve
address_offset : 0x928 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURVEA : ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor B-233 or K-233, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor B-283 or K-283, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_08\nFor B-409 or K-409, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_12\nFor B-571 or K-571, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_17\nFor P-192, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_05\nFor P-224, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_06\nFor P-256, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_07\nFor P-384, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_11\nFor P-521, CURVEA is stored in CRYPTO_ECC_A_00~CRYPTO_ECC_A_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the Parameter CURVEA Word1 of Elliptic Curve
address_offset : 0x92C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word2 of Elliptic Curve
address_offset : 0x930 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word3 of Elliptic Curve
address_offset : 0x934 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word4 of Elliptic Curve
address_offset : 0x938 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word5 of Elliptic Curve
address_offset : 0x93C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word6 of Elliptic Curve
address_offset : 0x940 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word7 of Elliptic Curve
address_offset : 0x944 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word8 of Elliptic Curve
address_offset : 0x948 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word9 of Elliptic Curve
address_offset : 0x94C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word10 of Elliptic Curve
address_offset : 0x950 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word11 of Elliptic Curve
address_offset : 0x954 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word12 of Elliptic Curve
address_offset : 0x958 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word13 of Elliptic Curve
address_offset : 0x95C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word14 of Elliptic Curve
address_offset : 0x960 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word15 of Elliptic Curve
address_offset : 0x964 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word16 of Elliptic Curve
address_offset : 0x968 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEA Word17 of Elliptic Curve
address_offset : 0x96C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word0 of Elliptic Curve
address_offset : 0x970 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURVEB : ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA)\nFor B-163 or K-163, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor B-233 or K-233, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor B-283 or K-283, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_08\nFor B-409 or K-409, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_12\nFor B-521 or K-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_17\nFor P-192, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_05\nFor P-224, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_06\nFor P-256, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_07\nFor P-384, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_11\nFor P-521, CURVEB is stored in CRYPTO_ECC_B_00~CRYPTO_ECC_B_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the Parameter CURVEB Word1 of Elliptic Curve
address_offset : 0x974 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word2 of Elliptic Curve
address_offset : 0x978 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word3 of Elliptic Curve
address_offset : 0x97C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word4 of Elliptic Curve
address_offset : 0x980 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word5 of Elliptic Curve
address_offset : 0x984 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word6 of Elliptic Curve
address_offset : 0x988 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word7 of Elliptic Curve
address_offset : 0x98C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word8 of Elliptic Curve
address_offset : 0x990 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word9 of Elliptic Curve
address_offset : 0x994 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word10 of Elliptic Curve
address_offset : 0x998 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word11 of Elliptic Curve
address_offset : 0x99C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word12 of Elliptic Curve
address_offset : 0x9A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word13 of Elliptic Curve
address_offset : 0x9A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word14 of Elliptic Curve
address_offset : 0x9A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word15 of Elliptic Curve
address_offset : 0x9AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word16 of Elliptic Curve
address_offset : 0x9B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEB Word17 of Elliptic Curve
address_offset : 0x9B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word0 of Elliptic Curve
address_offset : 0x9B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURVEN : ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN)\nIn GF(p), CURVEN is the prime p.\nIn GF(2m), CURVEN is the irreducible polynomial.\nFor B-163 or K-163, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor B-233 or K-233, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07\nFor B-283 or K-283, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_08\nFor B-409 or K-409, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_12\nFor B-571 or K-571, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_17\nFor P-192, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_05\nFor P-224, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_06\nFor P-256, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_07\nFor P-384, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_11\nFor P-521, CURVEN is stored in CRYPTO_ECC_N_00~CRYPTO_ECC_N_16
bits : 0 - 31 (32 bit)
access : read-write
ECC the Parameter CURVEN Word1 of Elliptic Curve
address_offset : 0x9BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word2 of Elliptic Curve
address_offset : 0x9C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word3 of Elliptic Curve
address_offset : 0x9C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word4 of Elliptic Curve
address_offset : 0x9C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word5 of Elliptic Curve
address_offset : 0x9CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word6 of Elliptic Curve
address_offset : 0x9D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word7 of Elliptic Curve
address_offset : 0x9D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word8 of Elliptic Curve
address_offset : 0x9D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word9 of Elliptic Curve
address_offset : 0x9DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word10 of Elliptic Curve
address_offset : 0x9E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word11 of Elliptic Curve
address_offset : 0x9E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word12 of Elliptic Curve
address_offset : 0x9E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word13 of Elliptic Curve
address_offset : 0x9EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word14 of Elliptic Curve
address_offset : 0x9F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word15 of Elliptic Curve
address_offset : 0x9F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word16 of Elliptic Curve
address_offset : 0x9F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Parameter CURVEN Word17 of Elliptic Curve
address_offset : 0x9FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word0 of Point Multiplication
address_offset : 0xA00 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SCALARK : ECC the Scalar SCALARK Value of Point Multiplication(SCALARK)\nBecause the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK.\nFor B-163 or K-163, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor B-233 or K-233, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07\nFor B-283 or K-283, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_08\nFor B-409 or K-409, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_12\nFor B-571 or K-571, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_17\nFor P-192, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_05\nFor P-224, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_06\nFor P-256, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_07\nFor P-384, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_11\nFor P-521, SCALARK is stored in CRYPTO_ECC_K_00~CRYPTO_ECC_K_16
bits : 0 - 31 (32 bit)
access : write-only
ECC the Scalar SCALARK Word1 of Point Multiplication
address_offset : 0xA04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word2 of Point Multiplication
address_offset : 0xA08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word3 of Point Multiplication
address_offset : 0xA0C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word4 of Point Multiplication
address_offset : 0xA10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word5 of Point Multiplication
address_offset : 0xA14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word6 of Point Multiplication
address_offset : 0xA18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word7 of Point Multiplication
address_offset : 0xA1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word8 of Point Multiplication
address_offset : 0xA20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word9 of Point Multiplication
address_offset : 0xA24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word10 of Point Multiplication
address_offset : 0xA28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word11 of Point Multiplication
address_offset : 0xA2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word12 of Point Multiplication
address_offset : 0xA30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word13 of Point Multiplication
address_offset : 0xA34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word14 of Point Multiplication
address_offset : 0xA38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word15 of Point Multiplication
address_offset : 0xA3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word16 of Point Multiplication
address_offset : 0xA40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC the Scalar SCALARK Word17 of Point Multiplication
address_offset : 0xA44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC DMA Source Address Register
address_offset : 0xA48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECC DMA Destination Address Register
address_offset : 0xA4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DADDR : ECC DMA Destination Address \nThe ECC accelerator supports DMA function to transfer the DATA and PARAMETER between SRAM memory and ECC accelerator. The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored. Based on the destination address, the ECC accelerator can write the result data back to SRAM memory space after the ECC operation is finished. The start of destination address should be located at word boundary. That is, bit 1 and 0 of DADDR are ignored. DADDR can be read and written. In DMA mode, software must update the CRYPTO_ECC_DADDR before triggering START.
bits : 0 - 31 (32 bit)
access : read-write
ECC Starting Address of Updated Registers
address_offset : 0xA50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTREG : ECC Starting Address of Updated Registers\nThe address of the updated registers that DMA feeds the first data or parameter to ECC engine. When ECC engine is active, ECC accelerator does not allow users to modify STARTREG, for example, to update input data from register CRYPTO_ECC POINTX1. Thus, the value of STARTREG is 0x808.
bits : 0 - 31 (32 bit)
access : read-write
ECC DMA Word Count
address_offset : 0xA54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WORDCNT : ECC DMA Word Count \nThe CRYPTO_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode. Although CRYPTO_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words. CRYPTO_ECC_WORDCNT can be read and written.
bits : 0 - 31 (32 bit)
access : read-write
Seed for PRNG
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SEED : Seed for PRNG (Write Only)\nThe bits store the seed for PRNG engine.
bits : 0 - 31 (32 bit)
access : write-only
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