Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x130 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
EADC Data Register 0 for Sample Module 0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : EADC Conversion Result\nThis field contains 12 bits conversion result.\nWhen DMOF (EADC_CTL[9]) is set to 0, 12-bit EADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].\nWhen DMOF (EADC_CTL[9]) set to 1, 12-bit EADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
bits : 0 - 15 (16 bit)
access : read-only
OV : Overrun Flag\nIf converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.\nNote: It is cleared by hardware after EADC_DAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[11:0] is recent conversion result
#1 : 1
Data in RESULT[11:0] is overwrite
End of enumeration elements list.
VALID : Valid Flag\nThis bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT[11:0] bits is not valid
#1 : 1
Data in RESULT[11:0] bits is valid
End of enumeration elements list.
EADC Data Register 4 for Sample Module 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Double Data Register 0 for Sample Module 0
address_offset : 0x100 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RESULT : EADC Conversion Results\nThis field contains 12 bits conversion results.\nWhen the DMOF (EADC_CTL[9]) is set to 0, 12-bit EADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].\nWhen DMOF (EADC_CTL[9]) is set to 1, 12-bit EADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
bits : 0 - 15 (16 bit)
access : read-only
OV : Overrun Flag\nIf converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1. It is cleared by hardware after EADC_DDAT register is read.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result
#1 : 1
Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite
End of enumeration elements list.
VALID : Valid Flag\n
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
Double data in RESULT (EADC_DDATn[15:0]) is not valid
#1 : 1
Double data in RESULT (EADC_DDATn[15:0]) is valid
End of enumeration elements list.
EADC Double Data Register 1 for Sample Module 1
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Double Data Register 2 for Sample Module 2
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Double Data Register 3 for Sample Module 3
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Power Management Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWUPRDY : EADC Power-up Sequence Completed and Ready for Conversion (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
EADC is not ready for conversion may be in power down state or in the progress of start up
#1 : 1
EADC is ready for conversion
End of enumeration elements list.
PWUCALEN : Power Up Calibration Function Enable Bit\nNote: This bit work together with CALSEL (EADC_CALCTL [3]), see the following\n{PWUCALEN, CALSEL } Description:\nPWUCALEN is 0 and CALSEL is 0: No need to calibrate. \nPWUCALEN is 0 and CALSEL is 1: No need to calibrate.\nPWUCALEN is 1 and CALSEL is 0: Load calibration word when power up.\nPWUCALEN is 1 and CALSEL is 1: Calibrate when power up.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Calibration function Disabled at power up
#1 : 1
Calibration function Enabled at power up
End of enumeration elements list.
PWDMOD : EADC Power-down Mode\nSet this bit field to select EADC Power-down mode when system power-down.\nNote: Different PWDMOD has different power down/up sequence, in order to avoid EADC powering up with wrong sequence; user must keep PWDMOD consistent each time in power down and start up.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
EADC Deep Power-down mode
#01 : 1
EADC Power down
#10 : 2
EADC Standby mode
#11 : 3
EADC Deep Power-down mode
End of enumeration elements list.
LDOSUT : EADC Internal LDO Start-up Time\n
bits : 8 - 19 (12 bit)
access : read-write
EADC Calibration Control Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALSTART : Calibration Functional Block Start\nNote 1: This bit is set by SW and clear by HW after re-calibration finish.\nNote 2: Before set CALSTART (EADC_CALCTL[1]) as 1 to start calibration again, EADCDIV (CKL_CLKDIV0[23:16]) must be 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stop calibration functional block
#1 : 1
Start calibration functional block
End of enumeration elements list.
CALDONE : Calibration Functional Block Complete (Read Only)\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#0 : 0
During a calibration
#1 : 1
Calibration is completed
End of enumeration elements list.
CALSEL : Select Calibration Functional Block\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Load calibration word when calibration functional block is active
#1 : 1
Execute calibration when calibration functional block is active
End of enumeration elements list.
EADC Calibration Load Word Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALWORD : Calibration Word Bits\nWrite to this register with the previous calibration word before load calibration action.\nRead this register after calibration done.\nNote: The calibration block contains two parts "CALIBRATION" and "LOAD CALIBRATION"; if the calibration block configure as "CALIBRATION"; then this register represent the result of calibration when calibration is completed; if configure as "LOAD CALIBRATION" ; configure this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the EADC; while in loading calibration function the loaded value will not be equal to the original CALWORD until calibration is done.
bits : 0 - 6 (7 bit)
access : read-write
EADC PDMA Control Register
address_offset : 0x130 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMATEN : PDMA Transfer Enable Bit\nWhen EADC conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.\n
bits : 0 - 18 (19 bit)
access : read-write
Enumeration:
0 : 0
PDMA data transfer Disabled
1 : 1
PDMA data transfer Enabled
End of enumeration elements list.
EADC Data Register 5 for Sample Module 5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 6 for Sample Module 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 7 for Sample Module 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 8 for Sample Module 8
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 9 for Sample Module 9
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 10 for Sample Module 10
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 11 for Sample Module 11
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 12 for Sample Module 12
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 13 for Sample Module 13
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 14 for Sample Module 14
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 15 for Sample Module 15
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 1 for Sample Module 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 16 for Sample Module 16
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 17 for Sample Module 17
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 18 for Sample Module 18
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC PDMA Current Transfer Data Register
address_offset : 0x4C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURDAT : EADC PDMA Current Transfer Data (Read Only)\n
bits : 0 - 17 (18 bit)
access : read-only
EADC Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCEN : EADC Converter Enable Bit\nNote: Before starting EADC conversion function, this bit should be set to 1. Clear it to 0 to disable EADC converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled EADC
#1 : 1
Enabled EADC
End of enumeration elements list.
ADCRST : EADC Converter Control Circuits Reset\nNote: EADCRST bit remains 1 during EADC reset, when EADC reset end, the EADCRST bit is automatically cleared to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Cause EADC control circuits reset to initial state, but not change the EADC registers value
End of enumeration elements list.
ADCIEN0 : Specific Sample Module EADC ADINT0 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module EADC conversion. If EADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module EADC ADINT0 interrupt function Disabled
#1 : 1
Specific sample module EADC ADINT0 interrupt function Enabled
End of enumeration elements list.
ADCIEN1 : Specific Sample Module EADC ADINT1 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module EADC conversion. If EADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module EADC ADINT1 interrupt function Disabled
#1 : 1
Specific sample module EADC ADINT1 interrupt function Enabled
End of enumeration elements list.
ADCIEN2 : Specific Sample Module EADC ADINT2 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module EADC conversion. If EADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module EADC ADINT2 interrupt function Disabled
#1 : 1
Specific sample module EADC ADINT2 interrupt function Enabled
End of enumeration elements list.
ADCIEN3 : Specific Sample Module EADC ADINT3 Interrupt Enable Bit\nThe EADC converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module EADC conversion. If EADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Specific sample module EADC ADINT3 interrupt function Disabled
#1 : 1
Specific sample module EADC ADINT3 interrupt function Enabled
End of enumeration elements list.
RESSEL : Resolution Selection\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
6-bit EADC result will be put at RESULT (EADC_DATn[5:0])
#01 : 1
8-bit EADC result will be put at RESULT (EADC_DATn[7:0])
#10 : 2
10-bit EADC result will be put at RESULT (EADC_DATn[9:0])
#11 : 3
12-bit EADC result will be put at RESULT (EADC_DATn[11:0])
End of enumeration elements list.
DIFFEN : Differential Analog Input Mode Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Single-end analog input mode
#1 : 1
Differential analog input mode
End of enumeration elements list.
DMOF : EADC Differential Input Mode Output Format\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with unsigned format
#1 : 1
EADC conversion result will be filled in RESULT (EADC_DATn[15:0], where n= 0 ~18) with 2'complement format
End of enumeration elements list.
EADC Sample Module Software Start Register
address_offset : 0x54 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SWTRG : EADC Sample Module 0~18 Software Force to Start EADC Conversion\nNote: After writing this register to start EADC conversion, the EADC_PENDSTS register will show which sample module will conversion. If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
bits : 0 - 18 (19 bit)
access : write-only
Enumeration:
0 : 0
No effect
1 : 1
Cause an EADC conversion when the priority is given to sample module
End of enumeration elements list.
EADC Start of Conversion Pending Flag Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STPF : EADC Sample Module 0~18 Start of Conversion Pending Flag\nRead Operation:\n
bits : 0 - 18 (19 bit)
access : read-write
Enumeration:
0 : 0
There is no pending conversion for sample module
1 : 1
Sample module EADC start of conversion is pending.\nCear pending flag & cancel the conversion for sample module
End of enumeration elements list.
EADC Sample Module Start of Conversion Overrun Flag Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPOVF : EADC SAMPLE0~18 Overrun Flag\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 18 (19 bit)
access : read-write
Enumeration:
0 : 0
No sample module event overrun
1 : 1
Indicates a new sample module event is generated while an old one event is pending
End of enumeration elements list.
EADC Data Register 2 for Sample Module 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 0 Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : EADC Sample Module Channel Selection\n
bits : 0 - 3 (4 bit)
access : read-write
EXTREN : EADC External Trigger Rising Edge Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge Disabled when EADC selects EADC0_ST as trigger source
#1 : 1
Rising edge Enabled when EADC selects EADC0_ST as trigger source
End of enumeration elements list.
EXTFEN : EADC External Trigger Falling Edge Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge Disabled when EADC selects EADC0_ST as trigger source
#1 : 1
Falling edge Enabled when EADC selects EADC0_ST as trigger source
End of enumeration elements list.
TRGDLYDIV : EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency: \n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
EADC_CLK/1
#01 : 1
EADC_CLK/2
#10 : 2
EADC_CLK/4
#11 : 3
EADC_CLK/16
End of enumeration elements list.
TRGDLYCNT : EADC Sample Module Start of Conversion Trigger Delay Time\n
bits : 8 - 15 (8 bit)
access : read-write
TRGSEL : EADC Sample Module Start of Conversion Trigger Source Selection\n
bits : 16 - 20 (5 bit)
access : read-write
INTPOS : Interrupt Flag Position Select\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion
#1 : 1
Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion
End of enumeration elements list.
DBMEN : Double Buffer Mode Enable Bit\n
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample has one sample result register (default)
#1 : 1
Sample has two sample result registers
End of enumeration elements list.
EXTSMPT : EADC Sampling Time Extend\nWhen EADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend EADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write
EADC Sample Module 1 Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 2 Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 3 Control Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 4 Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHSEL : EADC Sample Module Channel Selection\n
bits : 0 - 3 (4 bit)
access : read-write
EXTREN : EADC External Trigger Rising Edge Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge Disabled when EADC selects EADC0_ST as trigger source
#1 : 1
Rising edge Enabled when EADC selects EADC0_ST as trigger source
End of enumeration elements list.
EXTFEN : EADC External Trigger Falling Edge Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Falling edge Disabled when EADC selects EADC0_ST as trigger source
#1 : 1
Falling edge Enabled when EADC selects EADC0_ST as trigger source
End of enumeration elements list.
TRGDLYDIV : EADC Sample Module Start of Conversion Trigger Delay Clock Divider Selection\nTrigger delay clock frequency:\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
EADC_CLK/1
#01 : 1
EADC_CLK/2
#10 : 2
EADC_CLK/4
#11 : 3
EADC_CLK/16
End of enumeration elements list.
TRGDLYCNT : EADC Sample Module Start of Conversion Trigger Delay Time\n
bits : 8 - 15 (8 bit)
access : read-write
TRGSEL : EADC Sample Module Start of Conversion Trigger Source Selection\n
bits : 16 - 20 (5 bit)
access : read-write
INTPOS : Interrupt Flag Position Select\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC end of conversion
#1 : 1
Set ADIFn (EADC_STATUS2[n], n=0~3) at EADC start of conversion
End of enumeration elements list.
EXTSMPT : EADC Sampling Time Extend\nWhen EADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend EADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write
EADC Sample Module 5 Control Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 6 Control Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 7 Control Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 8 Control Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 9 Control Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 10 Control Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 11 Control Register
address_offset : 0xAC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 12 Control Register
address_offset : 0xB0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 13 Control Register
address_offset : 0xB4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 14 Control Register
address_offset : 0xB8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 15 Control Register
address_offset : 0xBC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Data Register 3 for Sample Module 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 16 Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTSMPT : EADC Sampling Time Extend\nWhen EADC converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend EADC sampling time after trigger source is coming to get enough sampling time.\nThe range of start delay time is from 0~255 EADC clock.
bits : 24 - 31 (8 bit)
access : read-write
EADC Sample Module 17 Control Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Sample Module 18 Control Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Interrupt 0 Source Enable Control Register.
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPLIE0 : Sample Module 0 Interrupt Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 0 interrupt Disabled
#1 : 1
Sample Module 0 interrupt Enabled
End of enumeration elements list.
SPLIE1 : Sample Module 1 Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 1 interrupt Disabled
#1 : 1
Sample Module 1 interrupt Enabled
End of enumeration elements list.
SPLIE2 : Sample Module 2 Interrupt Enable Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 2 interrupt Disabled
#1 : 1
Sample Module 2 interrupt Enabled
End of enumeration elements list.
SPLIE3 : Sample Module 3 Interrupt Enable Bit\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 3 interrupt Disabled
#1 : 1
Sample Module 3 interrupt Enabled
End of enumeration elements list.
SPLIE4 : Sample Module 4 Interrupt Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 4 interrupt Disabled
#1 : 1
Sample Module 4 interrupt Enabled
End of enumeration elements list.
SPLIE5 : Sample Module 5 Interrupt Enable Bit\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 5 interrupt Disabled
#1 : 1
Sample Module 5 interrupt Enabled
End of enumeration elements list.
SPLIE6 : Sample Module 6 Interrupt Enable Bit\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 6 interrupt Disabled
#1 : 1
Sample Module 6 interrupt Enabled
End of enumeration elements list.
SPLIE7 : Sample Module 7 Interrupt Enable Bit\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 7 interrupt Disabled
#1 : 1
Sample Module 7 interrupt Enabled
End of enumeration elements list.
SPLIE8 : Sample Module 8 Interrupt Enable Bit\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 8 interrupt Disabled
#1 : 1
Sample Module 8 interrupt Enabled
End of enumeration elements list.
SPLIE9 : Sample Module 9 Interrupt Enable Bit\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 9 interrupt Disabled
#1 : 1
Sample Module 9 interrupt Enabled
End of enumeration elements list.
SPLIE10 : Sample Module 10 Interrupt Enable Bit\n
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 10 interrupt Disabled
#1 : 1
Sample Module 10 interrupt Enabled
End of enumeration elements list.
SPLIE11 : Sample Module 11 Interrupt Enable Bit\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 11 interrupt Disabled
#1 : 1
Sample Module 11 interrupt Enabled
End of enumeration elements list.
SPLIE12 : Sample Module 12 Interrupt Enable Bit\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 12 interrupt Disabled
#1 : 1
Sample Module 12 interrupt Enabled
End of enumeration elements list.
SPLIE13 : Sample Module 13 Interrupt Enable Bit\n
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 13 interrupt Disabled
#1 : 1
Sample Module 13 interrupt Enabled
End of enumeration elements list.
SPLIE14 : Sample Module 14 Interrupt Enable Bit\n
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 14 interrupt Disabled
#1 : 1
Sample Module 14 interrupt Enabled
End of enumeration elements list.
SPLIE15 : Sample Module 15 Interrupt Enable Bit\n
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 15 interrupt Disabled
#1 : 1
Sample Module 15 interrupt Enabled
End of enumeration elements list.
SPLIE16 : Sample Module 16 Interrupt Enable Bit\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 16 interrupt Disabled
#1 : 1
Sample Module 16 interrupt Enabled
End of enumeration elements list.
SPLIE17 : Sample Module 17 Interrupt Enable Bit\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 17 interrupt Disabled
#1 : 1
Sample Module 17 interrupt Enabled
End of enumeration elements list.
SPLIE18 : Sample Module 18 Interrupt Enable Bit\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sample Module 18 interrupt Disabled
#1 : 1
Sample Module 18 interrupt Enabled
End of enumeration elements list.
EADC Interrupt 1 Source Enable Control Register.
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Interrupt 2 Source Enable Control Register.
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Interrupt 3 Source Enable Control Register.
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Result Compare Register 0
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCMPEN : EADC Result Compare Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare Disabled
#1 : 1
Compare Enabled
End of enumeration elements list.
ADCMPIE : EADC Result Compare Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit EADC conversion result is less than the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit EADC conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one
End of enumeration elements list.
CMPSPL : Compare Sample Module Selection\n
bits : 3 - 7 (5 bit)
access : read-write
Enumeration:
#00000 : 0
Sample Module 0 conversion result EADC_DAT0 is selected to be compared
#00001 : 1
Sample Module 1 conversion result EADC_DAT1 is selected to be compared
#00010 : 2
Sample Module 2 conversion result EADC_DAT2 is selected to be compared
#00011 : 3
Sample Module 3 conversion result EADC_DAT3 is selected to be compared
#00100 : 4
Sample Module 4 conversion result EADC_DAT4 is selected to be compared
#00101 : 5
Sample Module 5 conversion result EADC_DAT5 is selected to be compared
#00110 : 6
Sample Module 6 conversion result EADC_DAT6 is selected to be compared
#00111 : 7
Sample Module 7 conversion result EADC_DAT7 is selected to be compared
#01000 : 8
Sample Module 8 conversion result EADC_DAT8 is selected to be compared
#01001 : 9
Sample Module 9 conversion result EADC_DAT9 is selected to be compared
#01010 : 10
Sample Module 10 conversion result EADC_DAT10 is selected to be compared
#01011 : 11
Sample Module 11 conversion result EADC_DAT11 is selected to be compared
#01100 : 12
Sample Module 12 conversion result EADC_DAT12 is selected to be compared
#01101 : 13
Sample Module 13 conversion result EADC_DAT13 is selected to be compared
#01110 : 14
Sample Module 14 conversion result EADC_DAT14 is selected to be compared
#01111 : 15
Sample Module 15 conversion result EADC_DAT15 is selected to be compared
#10000 : 16
Sample Module 16 conversion result EADC_DAT16 is selected to be compared
#10001 : 17
Sample Module 17 conversion result EADC_DAT17 is selected to be compared
#10010 : 18
Sample Module 18 conversion result EADC_DAT18 is selected to be compared
End of enumeration elements list.
CMPMCNT : Compare Match Count\n
bits : 8 - 11 (4 bit)
access : read-write
CMPWEN : Compare Window Mode Enable Bit\nNote: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
EADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched
#1 : 1
EADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. EADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched
End of enumeration elements list.
CMPDAT : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage transition without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write
EADC Result Compare Register 1
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Result Compare Register 2
address_offset : 0xE8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Result Compare Register 3
address_offset : 0xEC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EADC Status Register 0
address_offset : 0xF0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID : EADC_DAT0~15 Data Valid Flag\n
bits : 0 - 15 (16 bit)
access : read-only
OV : EADC_DAT0~15 Overrun Flag\n
bits : 16 - 31 (16 bit)
access : read-only
EADC Status Register 1
address_offset : 0xF4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VALID : EADC_DAT16~18 Data Valid Flag\n
bits : 0 - 2 (3 bit)
access : read-only
OV : EADC_DAT16~18 Overrun Flag\n
bits : 16 - 18 (3 bit)
access : read-only
EADC Status Register 2
address_offset : 0xF8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADIF0 : EADC ADINT0 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT0 interrupt pulse received
#1 : 1
ADINT0 interrupt pulse has been received
End of enumeration elements list.
ADIF1 : EADC ADINT1 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT1 interrupt pulse received
#1 : 1
ADINT1 interrupt pulse has been received
End of enumeration elements list.
ADIF2 : EADC ADINT2 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it. \nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT2 interrupt pulse received
#1 : 1
ADINT2 interrupt pulse has been received
End of enumeration elements list.
ADIF3 : EADC ADINT3 Interrupt Flag\nNote 1: This bit is cleared by writing 1 to it.\nNote 2:This bit indicates whether an EADC conversion of specific sample module has been completed
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No ADINT3 interrupt pulse received
#1 : 1
ADINT3 interrupt pulse has been received
End of enumeration elements list.
ADCMPF0 : EADC Compare 0 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP0 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP0 register setting
End of enumeration elements list.
ADCMPF1 : EADC Compare 1 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP1 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP1 register setting
End of enumeration elements list.
ADCMPF2 : EADC Compare 2 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP2 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP2 register setting
End of enumeration elements list.
ADCMPF3 : EADC Compare 3 Flag\nWhen the specific sample module EADC conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.\nNote: This bit is cleared by writing 1 to it.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in EADC_DAT does not meet EADC_CMP3 register setting
#1 : 1
Conversion result in EADC_DAT meets EADC_CMP3 register setting
End of enumeration elements list.
ADOVIF0 : EADC ADINT0 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT0 interrupt flag is not overwritten to 1
#1 : 1
ADINT0 interrupt flag is overwritten to 1
End of enumeration elements list.
ADOVIF1 : EADC ADINT1 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT1 interrupt flag is not overwritten to 1
#1 : 1
ADINT1 interrupt flag is overwritten to 1
End of enumeration elements list.
ADOVIF2 : EADC ADINT2 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT2 interrupt flag is not overwritten to 1
#1 : 1
ADINT2 interrupt flag is s overwritten to 1
End of enumeration elements list.
ADOVIF3 : EADC ADINT3 Interrupt Flag Overrun\nNote: This bit is cleared by writing 1 to it.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADINT3 interrupt flag is not overwritten to 1
#1 : 1
ADINT3 interrupt flag is overwritten to 1
End of enumeration elements list.
ADCMPO0 : EADC Compare 0 Output Status (Read Only)\nThe 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.\n
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT0 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT0 setting
End of enumeration elements list.
ADCMPO1 : EADC Compare 1 Output Status (Read Only)\nThe 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.\n
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT1 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT1 setting
End of enumeration elements list.
ADCMPO2 : EADC Compare 2 Output Status (Read Only)\nThe 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.\n
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT2 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT2 setting
End of enumeration elements list.
ADCMPO3 : EADC Compare 3 Output Status (Read Only)\nThe 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module. User can use it to monitor the external analog input pin voltage status.\n
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#0 : 0
Conversion result in EADC_DAT less than CMPDAT3 setting
#1 : 1
Conversion result in EADC_DAT great than or equal CMPDAT3 setting
End of enumeration elements list.
CHANNEL : Current Conversion Channel (Read Only)\n
bits : 16 - 20 (5 bit)
access : read-only
BUSY : Busy/Idle (Read Only)\n
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
#0 : 0
EADC is in idle state
#1 : 1
EADC is busy at conversion
End of enumeration elements list.
ADOVIF : All EADC Interrupt Flag Overrun Bits Check (Read Only)\nNote: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
#1 : 1
Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1
End of enumeration elements list.
STOVF : for All EADC Sample Module Start of Conversion Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any SPOVFn Flag is equal to 1.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1
#1 : 1
Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1
End of enumeration elements list.
AVALID : for All Sample Module EADC Result Data Register EADC_DAT Data Valid Flag Check (Read Only)\nNote: This bit will keep 1 when any VALIDn Flag is equal to 1.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1
#1 : 1
Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1
End of enumeration elements list.
AOV : for All Sample Module EADC Result Data Register Overrun Flags Check (Read Only)\nNote: This bit will keep 1 when any OVn Flag is equal to 1.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
#0 : 0
None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1
#1 : 1
Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1
End of enumeration elements list.
EADC Status Register 3
address_offset : 0xFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CURSPL : EADC Current Sample Module (Read Only)\nThis register shows the current EADC is controlled by which sample module control logic modules.\nIf the EADC is Idle, the bit filed will set to 0x1F.
bits : 0 - 4 (5 bit)
access : read-only
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