\n

OPA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OPA_CTL (CTL)

OPA_STATUS (STATUS)

OPA_CALCTL (CALCTL)

OPA_CALST (CALST)


OPA_CTL (CTL)

OP Amplifier Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_CTL OPA_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPEN0 OPEN1 OPEN2 OPDOEN0 OPDOEN1 OPDOEN2 OPDOIEN0 OPDOIEN1 OPDOIEN2

OPEN0 : OP Amplifier 0 Enable Bit\nNote: OP Amplifier 0 output needs wait stable 20 s after OPEN0 is set.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier0 Disabled

#1 : 1

OP amplifier0 Enabled

End of enumeration elements list.

OPEN1 : OP Amplifier 1 Enable Bit\nNote: OP Amplifier 1 output needs wait stable 20 s after OPEN1 is set.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier1 Disabled

#1 : 1

OP amplifier1 Enabled

End of enumeration elements list.

OPEN2 : OP Amplifier 2 Enable Bit\nNote: OP Amplifier 2 output needs wait stable 20 s after OPEN2 is set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier2 Disabled

#1 : 1

OP amplifier2 Enabled

End of enumeration elements list.

OPDOEN0 : OP Amplifier 0 Schmitt Trigger Non-inverting Buffer Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier0 schmitt trigger non-invert buffer Disabled

#1 : 1

OP amplifier0 schmitt trigger non-invert buffer Enabled

End of enumeration elements list.

OPDOEN1 : OP Amplifier 1 Schmitt Trigger Non-inverting Buffer Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier1 schmitt trigger non-invert buffer Disabled

#1 : 1

OP amplifier1 schmitt trigger non-invert buffer Enabled

End of enumeration elements list.

OPDOEN2 : OP Amplifier 2 Schmitt Trigger Non-inverting Buffer Enable Bit
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP amplifier2 schmitt trigger non-invert buffer Disabled

#1 : 1

OP amplifier2 schmitt trigger non-invert buffer Enabled

End of enumeration elements list.

OPDOIEN0 : OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN0 is set to 1, a comparator interrupt request is generated.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP Amplifier 0 digital output interrupt function Disabled

#1 : 1

OP Amplifier 0 digital output interrupt function Enabled

End of enumeration elements list.

OPDOIEN1 : OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN1 is set to 1, a comparator interrupt request is generated.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP Amplifier 1 digital output interrupt function Disabled

#1 : 1

OP Amplifier 1 digital output interrupt function Enabled

End of enumeration elements list.

OPDOIEN2 : OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Enable Bit\nNote: The OPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPDOIEN2 is set to 1, a comparator interrupt request is generated.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#0 : 0

OP Amplifier 2 digital output interrupt function Disabled

#1 : 1

OP Amplifier 2 digital output interrupt function Enabled

End of enumeration elements list.


OPA_STATUS (STATUS)

OP Amplifier Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_STATUS OPA_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPDO0 OPDO1 OPDO2 OPDOIF0 OPDOIF1 OPDOIF2

OPDO0 : OP Amplifier 0 Digital Output
bits : 0 - 0 (1 bit)
access : read-write

OPDO1 : OP Amplifier 1 Digital Output
bits : 1 - 1 (1 bit)
access : read-write

OPDO2 : OP Amplifier 2 Digital Output
bits : 2 - 2 (1 bit)
access : read-write

OPDOIF0 : OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag\nOPDOIF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

OPDOIF1 : OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag\nOPDOIF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

OPDOIF2 : OP Amplifier 2 Schmitt Trigger Digital Output Interrupt Flag\nOPDOIF2 interrupt flag is set by hardware whenever the OP amplifier 2 Schmitt trigger non-inverting buffer digital output changes state. This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write


OPA_CALCTL (CALCTL)

OP Amplifier Calibration Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OPA_CALCTL OPA_CALCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CALTRG0 CALTRG1 CALTRG2 CALCLK0 CALCLK1 CALCLK2 CALRVS0 CALRVS1 CALRVS2

CALTRG0 : OP Amplifier 0 Calibration Trigger Bit\nNote1: Before this bit is enabled, OPEN0 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote2: Hardware will auto clear this bit when calibration is finished.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Calibration is stopped

#1 : 1

Calibration is triggered

End of enumeration elements list.

CALTRG1 : OP Amplifier 1 Calibration Trigger Bit\nNote1: Before this bit is enabled, OPEN1 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote2: Hardware will auto clear this bit when calibration is finished.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Calibration is stopped

#1 : 1

Calibration is triggered

End of enumeration elements list.

CALTRG2 : OP Amplifier 2 Calibration Trigger Bit\nNote1: Before this bit is enabled, OPEN2 should be set and the internal high speed RC oscillator (HIRC) should be enabled in advance.\nNote2: Hardware will auto clear this bit when calibration is finished.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Calibration is stopped,

#1 : 1

Calibration is triggered

End of enumeration elements list.

CALCLK0 : OP Amplifier 0 Calibration Clock Rate Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

#00 : 0

1 kHz

#01 : 1

Reserved.

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

CALCLK1 : OP Amplifier 1 Calibration Clock Rate Selection
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

#00 : 0

1 kHz

#01 : 1

Reserved.

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

CALCLK2 : OP Amplifier 2 Calibration Clock Rate Selection
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#00 : 0

1 kHz

#01 : 1

Reserved.

#10 : 2

Reserved.

#11 : 3

Reserved.

End of enumeration elements list.

CALRVS0 : OPA0 Calibration Reference Voltage Selection
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREF is

#1 : 1

VREF from high vcm to low vcm

End of enumeration elements list.

CALRVS1 : OPA1 Calibration Reference Voltage Selection
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREF is

#1 : 1

VREF from high vcm to low vcm

End of enumeration elements list.

CALRVS2 : OPA2 Calibration Reference Voltage Selection
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#0 : 0

VREF is

#1 : 1

VREF from high vcm to low vcm

End of enumeration elements list.


OPA_CALST (CALST)

OP Amplifier Calibration Status Register
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OPA_CALST OPA_CALST read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DONE0 CALNS0 CALPS0 DONE1 CALNS1 CALPS1 DONE2 CALNS2 CALPS2

DONE0 : OP Amplifier 0 Calibration Done Status
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Calibrating

#1 : 1

Calibration Done

End of enumeration elements list.

CALNS0 : OP Amplifier 0 Calibration Result Status for NMOS
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.

CALPS0 : OP Amplifier 0 Calibration Result Status for PMOS
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.

DONE1 : OP Amplifier 1 Calibration Done Status
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

#0 : 0

Calibrating

#1 : 1

Calibration Done

End of enumeration elements list.

CALNS1 : OP Amplifier 1 Calibration Result Status for NMOS
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.

CALPS1 : OP Amplifier 1 Calibration Result Status for PMOS
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.

DONE2 : OP Amplifier 2 Calibration Done Status
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

#0 : 0

Calibrating

#1 : 1

Calibration Done

End of enumeration elements list.

CALNS2 : OP Amplifier 2 Calibration Result Status for NMOS
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.

CALPS2 : OP Amplifier 2 Calibration Result Status for PMOS
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

#0 : 0

Pass

#1 : 1

Fail

End of enumeration elements list.



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