PDID

RegLockAddr

BODCR

LDOCR

LDOBPCR

PORCR

P0_MFP

P1_MFP

P2_MFP

P3_MFP

RSTSRC

P4_MFP

P5_MFP

IPRSTC1

IRCTRIMCTL

IRCTRIMIEN

IRCTRIMINT

IPRSTC2

PDID : Product Device Identification Number This register reflects the device part number code. Software can read this register to identify which device is used. For example, the MINI51LBN PDID code is 0x10205100 .
bits : 0 - 31 (32 bit)
access : read-only

RegUnLock : The Protected registers are:\nIPRSTC1 - address 0x5000_0008 (IP reset control register 1)\nBODCR - address 0x5000_0018 (Brown-out detector control register)\nLDOCR - address 0x5000_001C (LDO control register)\nPORCR - address 0x5000_0024 (Power-On-Reset control register)\nPWRCON - address 0x5000_0200 (bit[6] is not protected for power wake-up interrupt clear)\nAPBCLK[0] - address 0x5000_0208 (Watchdog clock enable)\nCLKSEL0 - address 0x5000_0210 (HCLK and CPU STCLK clock source select)\nCLKSEL1[1:0] - address 0x5000_0214 (Watchdog clock source select)\nNMI_SEL[8] - address 0x5000_380 (NMI interrupt source enable)\nISPCON - address 0x5000_C000 (Flash ISP control register)\nWTCR - address 0x4000_4000 (Watchdog Timer control register)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_VL : Brown-out Detector Threshold Voltage Selection (Initiated Write-protected bit)
bits : 1 - 2 (2 bit)
access : read-write

BOD_RSTEN : Brown-out Reset Enable (Initiated and Write-protected bit)\nWhen the BOD_EN is enabled and the interrupt is asserted, the interrupt will be kept till the BOD_EN is set to 0. The interrupt for CPU can be blocked by disabling the NVIC in CPU for BOD interrupt or disable the interrupt source by disabling the BOD_EN and then re-enabling the BOD_EN function if the BOD function is required.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INTF : Brown-out Detector Interrupt Flag\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_OUT : Brown-out Detector Output State\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P0_MFP : P0 Multiple Function Selection\nThe pin function of P0 depends on P0_MFP and P0_ALT.\nRefer to P0_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P0_ALT0 : P0.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P0_ALT1 : P0.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P0_ALT4 : P0.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P0_ALT5 : P0.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P0_ALT6 : P0.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P0_ALT7 : P0.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P0_TYPE : P0[7:0] Input Schmitt Trigger Function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P1_MFP : P1 Multiple Function Selection\nThe pin function of P1 depends on P1_MFP and P1_ALT.\nRefer to P1_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P1_ALT0 : P1.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P1_ALT2 : P1.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P1_ALT3 : P1.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P1_ALT4 : P1.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P1_ALT5 : P1.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P1_TYPE : P1[7:0] Input Schmitt Trigger Function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P2_MFP : P2 Multiple Function Selection\nThe pin function of P2 depends on P2_MFP and P2_ALT.\nRefer to P2_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P2_ALT2 : P2.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P2_ALT3 : P2.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P2_ALT4 : P2.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P2_ALT5 : P2.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P2_ALT6 : P2.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P2_TYPE : P2[7:0] Input Schmitt Trigger Function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P3_MFP : P3 Multiple Function Selection\nThe pin function of P3 depends on P3_MFP and P3_ALT.\nRefer to P3_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P3_ALT0 : P3.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P3_ALT1 : P3.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P3_ALT2 : P3.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P3_ALT4 : P3.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P3_ALT5 : P3.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P3_ALT6 : P3.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P3_TYPE : P3[7:0] Input Schmitt Trigger Function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P32CPP1 : P3.2 Alternate Function Selection Extension\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_POR : The RSTS_POR flag is set by the reset signal , which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) set, to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_RESET : The RSTS_RESET flag is set by the reset signal from the /RESET pin to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDT : The RSTS_WDT flag is set by the reset signal from the Watchdog module to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_BOD : The RSTS_BOD flag is set by the reset signal from the Brown-out Detected module to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_MCU : The RSTS_MCU flag is set by the reset signal from the Cortex-M0 kernel to indicate the previous reset source. Software can write 1 to clear this bit to zero.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) with 1 to reset the Cortex-M0 CPU kernel and Flash Memory Controller (FMC).\nSoftware can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P4_MFP : P4 Multiple Function Selection\nThe pin function of P4 depends on P4_MFP and P4_ALT.\nRefer to P4_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P4_ALT6 : P4.6 Alternate Function Selection\n
bits : 14 - 14 (1 bit)
access : read-write

P4_ALT7 : P4.7 Alternate Function Selection\n
bits : 15 - 15 (1 bit)
access : read-write

P4_TYPE : P4[7:0] Input Schmitt Trigger Function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

P5_MFP : P5 Multiple Function Selection\nThe pin function of P5 depends on P5_MFP and P5_ALT.\nRefer to P5_ALT Description for details.
bits : 0 - 7 (8 bit)
access : read-write

P5_ALT0 : P5.0 Alternate Function Selection\n
bits : 8 - 8 (1 bit)
access : read-write

P5_ALT1 : P5.1 Alternate Function Selection\n
bits : 9 - 9 (1 bit)
access : read-write

P5_ALT2 : P5.2 Alternate Function Selection\n
bits : 10 - 10 (1 bit)
access : read-write

P5_ALT3 : P5.3 Alternate Function Selection\n
bits : 11 - 11 (1 bit)
access : read-write

P5_ALT4 : P5.4 Alternate Function Selection\n
bits : 12 - 12 (1 bit)
access : read-write

P5_ALT5 : P5.5 Alternate Function Selection\n
bits : 13 - 13 (1 bit)
access : read-write

P5_TYPE : P5[7:0] Input Schmitt Trigger Function Enable\n
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIP_RST : CHIP One Shot Reset\nSetting this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIP_RST is the same as the POR reset, and all the chip module is reset and the chip settings from flash are also reload.\nThis bit is the protected bit, and programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : CPU Kernel One Shot Reset\nSetting this bit will reset the CPU kernel, and this bit will automatically return to 0 after the 2 clock cycles.\nThis bit is the protected bit, programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_SEL : Trim Frequency Selection\nThis bit is to enable the HFIRC auto trim.\nWhen setting this bit to 1, the HFIRC auto trim function will trim HFIRC to 22.1184 MHz automatically based on the LXT reference clock.\nDuring auto trim operation, if LXT clock error is detected or trim retry limitation count reached, this field will be cleared to 0 automatically.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_LOOP : Trim Calculation Loop This field defines trim value calculation based on the number of LXT clock. For example, if TRIM_LOOP is set as 00 , auto trim circuit will calculate trim value based on the average frequency difference in 4 LXT clock. This field also defines how many times the auto trim circuit will try to update the HFIRC trim value before the frequency of HFIRC is locked. Once the HFIRC is locked, the internal trim value update counter will be reset. If the trim value update counter reaches this limitation value and frequency of HFIRC is still not locked, the auto trim operation will be disabled and TRIM_SEL will be cleared to 0.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_FAIL_IEN : Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HFIRC trim value update limitation count is reached and HFIRC frequency is still not locked on target frequency set by TRIM_SEL.\nIf this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be triggered to notify that HFIRC trim value update limitation count is reached.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

_32K_ERR_IEN : LXT Clock Error Interrupt Enable\nThis bit controls if CPU could get an interrupt while LXT clock is inaccurate during auto trim operation.\nIf this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered to notify the LXT clock frequency is inaccurate.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ_LOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TRIM_FAIL_INT : Trim Failure Interrupt Status\nThis bit indicates that HFIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify that HFIRC trim value update limitation count was reached. Software can write 1 to clear this bit to zero.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

_32K_ERR_INT : LXT Clock Error Interrupt Status\nThis bit indicates that LXT clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL will be cleared to 0 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the LXT clock frequency is inaccuracy. Software can write 1 to clear this bit to zero.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_RST : GPIO (P0~P5) Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C_RST : I2C Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI_RST : SPI Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART_RST : UART Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM_RST : PWM Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ACMP_RST : ACMP Controller Reset\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.