Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x24 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
System Power-down Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTLCLK_EN : External HXT or LXT Crystal Oscillator Control
The default clock source is from HIRC. These two bits are default set to 00 and the XTAL1 and XTAL2 pins are GPIO.
Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
XTAL1 and XTAL2 are GPIO, disable both LXT HXT (default)
#01 : 1
HXT Enabled
#10 : 2
LXT Enabled
#11 : 3
XTAL1 is external clock input pin, XTAL2 is GPIO
End of enumeration elements list.
OSC22M_EN : HIRC Control\nNote: The default of OSC22M_EN bit is 1.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC oscillator Disabled
#1 : 1
HIRC oscillator Enabled
End of enumeration elements list.
OSC10K_EN : LIRC Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIRC oscillator Disabled
#1 : 1
LIRC oscillator Enabled
End of enumeration elements list.
WU_DLY : Wake-up Delay Counter Enable (Write-protected)\nWhen the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip work at HXT, 4096 clock cycle for LXT, and 16 clock cycles when chip work at HIRC oscillator.\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock cycles delay Disabled
#1 : 1
Clock cycles delay Enabled
End of enumeration elements list.
PD_WU_INT_EN : Power-down Mode Wake-up Interrupt Enable (Write-protected)\nThe interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled. The interrupt will occur when Power-down mode wake up
End of enumeration elements list.
PD_WU_STS : Power-down Mode Wake-up Interrupt Status
When set by power-down wake-up event , it indicates that resume from Power-down mode.
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wake-up occurred.
Software can write 1 to clear the bit to zero.
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) is set to 1.
bits : 6 - 6 (1 bit)
access : read-write
PWR_DOWN_EN : System Power-down Active or Enable Bit\nWhen chip waked up from power-down, this bit is automatically cleared, and user needs to set this bit again for the next power-down.\nIn Power-down mode, the LDO, external crystal and the HIRC will be disabled, and the LIRC enable is not controlled by this bit.\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip operated in Normal mode or CPU enters into Idle mode
#1 : 1
Chip entering the Power-down mode instantly or wait CPU Idle command
End of enumeration elements list.
PD_32K : This bit controls the crystal oscillator active or not in Power-down mode.\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect to Power-down mode
#1 : 1
If XTLCLK_EN[1:0] = 10, LXT is still active in Power-down mode
End of enumeration elements list.
Clock Source Select Control Register 0
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_S : HCLK Clock Source Selection
Note: Before clock switch the related clock sources (pre-select and new-select) must be turned on.
These bits are protected bit programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.
Note: To set PWRCON[1:0] to select HXT or LXT crystal clock.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT or LXT crystal clock
#001 : 1
Reserved
#010 : 2
Reserved
#011 : 3
Clock source from LIRC oscillator clock
#111 : 7
Clock source from HIRC oscillator clock
End of enumeration elements list.
STCLK_S : Cortex-M0 CPU SysTick Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 3 - 5 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT or LXT crystal clock
#001 : 1
Reserved
#010 : 2
Clock source from HXT or LXT crystal clock/2
#011 : 3
Clock source from HCLK/2
#111 : 7
Clock source from HIRC oscillator clock/2
End of enumeration elements list.
Clock Source Select Control Register 1
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_S : WDT CLK Clock Source Selection\nThese bits are protected bit, programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT or LXT crystal clock
#01 : 1
Reserved
#10 : 2
Clock source from HCLK/2048 clock
#11 : 3
Clock source from LIRC oscillator clock
End of enumeration elements list.
ADC_S : ADC Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT or LXT crystal clock
#01 : 1
Reserved
#10 : 2
Clock source from HCLK clock
#11 : 3
Clock source from HIRC oscillator clock
End of enumeration elements list.
TMR0_S : TIMER0 Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT or LXT crystal clock
#001 : 1
Clock source from LIRC oscillator clock
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger
#111 : 7
Clock source from HIRC oscillator clock
End of enumeration elements list.
TMR1_S : TIMER1 Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#000 : 0
Clock source from HXT or LXT crystal clock
#001 : 1
Clock source from LIRC oscillator clock
#010 : 2
Clock source from HCLK
#011 : 3
Clock source from external trigger
#111 : 7
Clock source from HIRC oscillator clock
End of enumeration elements list.
UART_S : UART Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT or LXT crystal clock
#01 : 1
Reserved
#10 : 2
Clock source from HIRC oscillator clock
#11 : 3
Reserved
End of enumeration elements list.
PWM01_S : PWM0 and PWM1 Clock Source Selection\nPWM0 and PWM1 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Reserved
End of enumeration elements list.
PWM23_S : PWM2 and PWM3 Clock Source Selection\nPWM2 and PWM3 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Reserved
End of enumeration elements list.
Clock Divider Number Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HCLK_N : HCLK Clock Divide Number from HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write
UART_N : UART Clock Divide Number from UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write
ADC_N : ADC Clock Divide Number from ADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write
Clock Source Select Control Register 2
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRQDIV_S : Clock Divider Clock Source Selection\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Clock source from HXT or LXT crystal clock
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Clock source from HIRC oscillator clock
End of enumeration elements list.
PWM45_S : PWM4 and PWM5 Clock Source Selection - PWM4 and PWM5 use the same Engine clock source. They both have the same pre-scalar.\nNote: To set PWRCON[1:0], select HXT or LXT crystal clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Reserved
#01 : 1
Reserved
#10 : 2
Clock source from HCLK
#11 : 3
Reserved
End of enumeration elements list.
Frequency Divider Control Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FSEL[3:0].
bits : 0 - 3 (4 bit)
access : read-write
DIVIDER_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Frequency Divider Disabled
#1 : 1
Frequency Divider Enabled
End of enumeration elements list.
AHB Device Clock Enable Control Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISP_EN : Flash ISP Controller Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash ISP engine clock Disabled
#1 : 1
Flash ISP engine clock Enabled
End of enumeration elements list.
APB Device Clock Enable Control Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT_EN : Watchdog Clock Enable
This bit is the protected bit programming this needs an open lock sequence, write 0x59, 0x16, 0x88 to address 0x5000_0100 to un-lock this bit. Refer to the register RegLockAddr at address GCR_BA + 0x100.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMR0_EN : Timer0 Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
TMR1_EN : Timer1 Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
FDIV_EN : Clock Divider Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
I2C_EN : I2C Clock Enable Control\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
SPI_EN : SPI Clock Enable Control\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
UART_EN : UART Clock Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Both the UART APB and the engine clock Disabled
#1 : 1
Both the UART APB and the engine clock Enabled
End of enumeration elements list.
PWM01_EN : PWM_01 Clock Enable Control\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Both the PWM01 APB and the engine clock Disabled
#1 : 1
Both the PWM01 APB and the engine clock Enabled
End of enumeration elements list.
PWM23_EN : PWM_23 Clock Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Both the PWM23 APB and the engine clock Disabled
#1 : 1
Both the PWM23 APB and the engine clock Enabled
End of enumeration elements list.
PWM45_EN : PWM_45 Clock Enable Control\n
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Both the PWM45 APB and the engine clock Disabled
#1 : 1
Both the PWM45 APB and the engine clock Enabled
End of enumeration elements list.
ADC_EN : Analog-Digital-Converter (ADC) Clock Enable Control\n
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Both the ADC's APB and the engine clock Disabled
#1 : 1
Both the ADC's APB and the engine clock Enabled
End of enumeration elements list.
CMP_EN : Comparator Clock Enable\n
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Analog Comparator Clock Disabled
#1 : 1
Analog Comparator Clock Enabled
End of enumeration elements list.
Clock Status Monitor Register
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTL_STB : HXT or LXT Clock Source Stable Flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HXT or LXT clock not stable or not enabled
#1 : 1
HXT or LXT clock stable
End of enumeration elements list.
OSC10K_STB : LIRC Clock Source Stable Flag\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
LIRC clock not stable or not enabled
#1 : 1
LIRC clock stable
End of enumeration elements list.
OSC22M_STB : HIRC Clock Source Stable Flag\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC clock not stable or not enabled
#1 : 1
HIRC clock stable
End of enumeration elements list.
CLK_SW_FAIL : Clock Switch Fail Flag\nThis bit will be set when target switch clock source is not stable.\nSoftware can write 1 to clear this bit to zero.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock switch success
#1 : 1
Clock switch failed
End of enumeration elements list.
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