Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Comparator0 Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP0EN : Comparator0 Enable\nComparator output needs to wait 10 us stable time after CMP0EN is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CMP0IE : Comparator0 Interrupt Enable\nInterrupt is generated if CMP0IE bit is set to 1 after CMP0 conversion finished.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP0 interrupt function Disabled
#1 : 1
CMP0 interrupt function Enabled
End of enumeration elements list.
CMP0_HYSEN : Comparator0 Hysteresis Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP0 Hysteresis function Disabled (Default)
#1 : 1
CMP0 Hysteresis function at comparator 0 Enabled that the typical range is 20mV
End of enumeration elements list.
CN0 : Comparator0 Negative Input Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The comparator reference pin CPN0 is selected as the negative comparator input
#1 : 1
The internal comparator reference voltage (Vref = 1.25V or from CRV setting value) is selected as the negative comparator input
End of enumeration elements list.
CMP0_RISING : Comparator0 Trigger PWM/Timer on Rising Edge Enable\nNote: The bit is only effective while comparator0 triggers PWM/Timer.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable comparator0 trigger PWM/Timer on rising edge
#1 : 1
Enable comparator0 trigger PWM/Timer on rising edge
End of enumeration elements list.
CMP0_FALLING : Comparator0 Falling Edge Trigger Enable\nNote: The bit is only effective while comparator0 triggers PWM/Timer.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable comparator0 trigger PWM/Timer on falling edge
#1 : 1
Enable comparator0 trigger PWM/Timer on falling edge
End of enumeration elements list.
CPP0SEL : Comparator0 Positive Input Selection\n
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
#00 : 0
From P1.5
#01 : 1
From P1.0
#10 : 2
From P1.2
#11 : 3
From P1.3
End of enumeration elements list.
Comparator1 Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMP1EN : Comparator1 Enable\nComparator output needs to wait 10 us stable time after CMP1EN is set.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CMP1IE : Comparator1 Interrupt Enable\nInterrupt is generated if CMP1IE bit is set to 1 after CMP1 conversion finished.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP1 interrupt function Disabled
#1 : 1
CMP1 interrupt function Enabled
End of enumeration elements list.
CMP1_HYSEN : Comparator1 Hysteresis Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
CMP0 Hysteresis function Disabled (Default)
#1 : 1
CMP0 Hysteresis function at comparator 0 Enabled that the typical range is 20mV
End of enumeration elements list.
CN1 : Comparator1 Negative Input Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The comparator reference pin CPN0 is selected as the negative comparator input
#1 : 1
The internal comparator reference voltage (Vref=1.25V or from CRV setting value) is selected as the negative comparator input
End of enumeration elements list.
CMP1_RISING : Comparator1 Trigger PWM/Timer on Rising Edge Enable\nNote: The bit is only effective while comparator1 triggers PWM/Timer.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable comparator1 trigger PWM/Timer on rising edge
#1 : 1
Enable comparator1 trigger PWM/Timer on rising edge
End of enumeration elements list.
CMP1_FALLING : Comparator1 Falling Edge Trigger Enable\nNote: The bit is only effective while comparator1 triggers PWM/Timer.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable comparator1 trigger PWM/Timer on falling edge
#1 : 1
Enable comparator1 trigger PWM/Timer on falling edge
End of enumeration elements list.
CPP1SEL : Comparator1 Positive Input Selection\n
bits : 29 - 30 (2 bit)
access : read-write
Enumeration:
#00 : 0
From P3.1
#01 : 1
From P3.2
#10 : 2
From P3.4
#11 : 3
From P3.5
End of enumeration elements list.
Comparator Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPF0 : Comparator0 Flag\nThis bit is set by hardware whenever the comparator0 output changes state. This will cause an interrupt if CMP0IE set.\nSoftware can write 1 to clear this bit to zero.
bits : 0 - 0 (1 bit)
access : read-write
CMPF1 : Comparator1 Flag\nThis bit is set by hardware whenever the comparator1 output changes state. This will cause an interrupt if CMP1IE set.\nSoftware can write 1 to clear this bit to zero.
bits : 1 - 1 (1 bit)
access : read-write
CO0 : Comparator0 Output\n
bits : 2 - 2 (1 bit)
access : read-write
CO1 : Comparator1 Output\n
bits : 3 - 3 (1 bit)
access : read-write
Comparator Reference Voltage Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRVS : Comparator Reference Voltage Setting\n
bits : 0 - 3 (4 bit)
access : read-write
OUT_SEL : CRV Module Output Selection\n
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Band-gap 1.22 V voltage Selected
#1 : 1
CRVS setting voltage Selected
End of enumeration elements list.
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