\n
address_offset : 0x0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x210 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x228 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x248 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x260 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x270 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x298 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
P0 Pin I/O Mode Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMD0 : Px Pin[n] I/O Mode Control\n
bits : 0 - 1 (2 bit)
access : read-write
PMD1 : Px Pin[n] I/O Mode Control\n
bits : 2 - 3 (2 bit)
access : read-write
PMD2 : Px Pin[n] I/O Mode Control\n
bits : 4 - 5 (2 bit)
access : read-write
PMD3 : Px Pin[n] I/O Mode Control\n
bits : 6 - 7 (2 bit)
access : read-write
PMD4 : Px Pin[n] I/O Mode Control\n
bits : 8 - 9 (2 bit)
access : read-write
PMD5 : Px Pin[n] I/O Mode Control\n
bits : 10 - 11 (2 bit)
access : read-write
PMD6 : Px Pin[n] I/O Mode Control\n
bits : 12 - 13 (2 bit)
access : read-write
PMD7 : Px Pin[n] I/O Mode Control\n
bits : 14 - 15 (2 bit)
access : read-write
P0 Pin Value
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN : Px Pin[n] Value\n
bits : 0 - 0 (1 bit)
access : read-only
P4 Pin I/O Mode Control
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Pin OFF Digital Enable
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Data Output Value
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Data Output Write Mask
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Pin Value
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 De-bounce Enable
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Mode Control
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Enable
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4 Interrupt Trigger Source Indicator
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 De-bounce Enable
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN : Px Input Signal De-bounce Enable
DBEN[n] is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle, the input signal transition is regarded as the signal bounce and will not trigger the interrupt.
The DBEN[n] is used for edge-trigger interrupt only, and is ignored for level trigger interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The pin[n] de-bounce function disabled
#1 : 1
The pin[n] de-bounce function enabled
End of enumeration elements list.
P5 Pin I/O Mode Control
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Pin OFF Digital Enable
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Data Output Value
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Data Output Write Mask
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Pin Value
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 De-bounce Enable
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Interrupt Mode Control
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Interrupt Enable
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5 Interrupt Trigger Source Indicator
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Interrupt Mode Control
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMD : Port 0-5 Interrupt Mode Control\nIMD[n] is used to control the interrupt by level trigger or edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounced. If the interrupt is by level trigger, the input source is sampled by one clock and then generates the interrupt.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
Interrupt De-bounce Cycle Control
address_offset : 0x180 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBCLKSEL : De-bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write
DBCLKSRC : De-bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter clock source is the HCLK
#1 : 1
De-bounce counter clock source is the internal 10 kHz clock
End of enumeration elements list.
ICLK_ON : Interrupt Clock On Mode\nSetting this bit to 0 will disable the interrupt generate circuit clock, if the pin[n] interrupt is disabled.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The clock Disabled if the P0/1/2/3/4[n] interrupt is disabled
#1 : 1
Interrupt generated circuit clock always Enabled
End of enumeration elements list.
P0 Interrupt Enable
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IF_EN : Port 0-5 Interrupt Enable by Input Falling Edge or Input Level Low
IF_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.
When the IF_EB[n] bit is set to 1:
If the interrupt is level mode trigger, the input Px[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state changed from high-to-low will generate the interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Px[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
The Px[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
IR_EN : Port 0-5 Interrupt Enable by Input Rising Edge or Input Level High
IR_EN[n] is used to enable the interrupt for each of the corresponding input Px[n]. Setting bit to 1 also enables the pin wake-up function.
When the IR_EN[n] bit is set to 1:
If the interrupt is level mode trigger, the input Px[n] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input Px[n] state changed from low-to-high will generate the interrupt.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
The Px[n] level-high or low-to-high interrupt Disabled
#1 : 1
The Px[n] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
P0 Interrupt Trigger Source Indicator
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISRC : Port 0-5 Interrupt Trigger Source Indicator\nRead :\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Px[n].\nNo action
#1 : 1
Indicates Px[n] generate an interrupt.\nClear the corresponding pending interrupt
End of enumeration elements list.
P0.0 Data Output Value
address_offset : 0x200 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P_DOUT : P[x][n] I/O Pin Bit Output/Input Control\nWriting this bit can control one GPIO pin output value.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO pin set to low.\nCorresponding GPIO pin status is low
#1 : 1
The corresponding GPIO pin set to high.\nCorresponding GPIO pin status is high
End of enumeration elements list.
P0.1 Data Output Value
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0.4 Data Output Value
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0.5 Data Output Value
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0.6 Data Output Value
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0.7 Data Output Value
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1.0 Data Output Value
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1.2 Data Output Value
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1.3 Data Output Value
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1.4 Data Output Value
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1.5 Data Output Value
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2.2 Data Output Value
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2.3 Data Output Value
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2.4 Data Output Value
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2.5 Data Output Value
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2.6 Data Output Value
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3.0 Data Output Value
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3.1 Data Output Value
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3.2 Data Output Value
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3.4 Data Output Value
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3.5 Data Output Value
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3.6 Data Output Value
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4.6 Data Output Value
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P4.7 Data Output Value
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5.0 Data Output Value
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5.1 Data Output Value
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5.2 Data Output Value
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5.3 Data Output Value
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5.4 Data Output Value
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P5.5 Data Output Value
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Pin OFF Digital Enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFD : OFFD: Px Pin[n] OFF Digital Input Path Enable\n
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : 0
I/O digital input path Enabled
1 : 1
I/O digital input path Disabled (digital input tied to low)
End of enumeration elements list.
P1 Pin I/O Mode Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Pin OFF Digital Enable
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Data Output Value
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Data Output Write Mask
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Pin Value
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 De-bounce Enable
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Mode Control
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Enable
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1 Interrupt Trigger Source Indicator
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Data Output Value
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT : Px Pin[n] Output Value\nEach of these bits controls the status of a Px pin when the Px pin is configures as output, open-drain and quasi-mode.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Px pin[n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
Px pin[n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
P2 Pin I/O Mode Control
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Pin OFF Digital Enable
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Data Output Value
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Data Output Write Mask
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Pin Value
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 De-bounce Enable
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Mode Control
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Enable
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P2 Interrupt Trigger Source Indicator
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0 Data Output Write Mask
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASK : Px Data Output Write Mask\nThese bits are used to protect the corresponding register of Px_DOUT pin[n]. When the DMASK bit[n] is set to 1, the corresponding DOUTn pin is protected. The write signal is masked, and writing data to the protect pin is ignored.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding Px_DOUT[n] bit can be updated
#1 : 1
The corresponding Px_DOUT[n] bit is protected
End of enumeration elements list.
P3 Pin I/O Mode Control
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Pin OFF Digital Enable
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Data Output Value
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Data Output Write Mask
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Pin Value
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 De-bounce Enable
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Mode Control
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Enable
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P3 Interrupt Trigger Source Indicator
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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