\n
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x280 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x400 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD00 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD0C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xD1C Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : System Tick Counter Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
System Tick counter Disabled
#1 : 1
System Tick counter will operate in a multi-shot manner
End of enumeration elements list.
TICKINT : System Tick Interrupt Enable Bit\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Counting down to 0 will not cause the SysTick exception to be pended. User can use COUNTFLAG to determine if a count to zero has occurred
#1 : 1
Counting down to 0 will cause the SysTick exception to be pended. Clearing the SysTick Current Value register by a register write in software will not cause SysTick to be pended
End of enumeration elements list.
CLKSRC : System Tick Clock Source Select Bit\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock source is optional, refer to STCLKSEL
#1 : 1
Core clock used for SysTick timer
End of enumeration elements list.
COUNTFLAG : System Tick Counter Flag\nReturn 1 If Timer Counted to 0 Since Last Time this Register Was Read\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
COUNTFLAG is cleared on read or by a write to the Current Value register
#1 : 1
COUNTFLAG is set by a count transition from 1 to 0
End of enumeration elements list.
IRQ0 ~ IRQ31 Set-enable Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Enable Register \nEnable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite operation:\nRead value indicates the current enable status.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nAssociated interrupt status Disabled
1 : 1
Write 1 to enable associated interrupt.\nAssociated interrupt status Enabled
End of enumeration elements list.
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : System Tick Reload Value\nValue to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : System Tick Current Value\nCurrent counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0.
bits : 0 - 23 (24 bit)
access : read-write
IRQ0 ~ IRQ31 Clear-enable Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Interrupt Disable Register\nDisable one or more interrupts. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWrite operation:\nNote: Read value indicates the current enable status.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nAssociated interrupt status Disabled
1 : 1
Write 1 to disable associated interrupt.\nAssociated interrupt status Enabled
End of enumeration elements list.
IRQ0 ~ IRQ31 Set-pending Control Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Set Interrupt Pending Register\nWrite operation:\nNote: Read value indicates the current pending status.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nAssociated interrupt in not in pending status
1 : 1
Write 1 to set pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
End of enumeration elements list.
IRQ0 ~ IRQ31 Clear-pending Control Register
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Clear Interrupt Pending Register\nWrite operation:\nNote: Read value indicates the current pending status.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nAssociated interrupt in not in pending status
1 : 1
Write 1 to clear pending state. Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nAssociated interrupt is in pending status
End of enumeration elements list.
IRQ0 ~ IRQ3 Interrupt Priority Control Register
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority of IRQ0\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_1 : Priority of IRQ1\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_2 : Priority of IRQ2\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_3 : Priority of IRQ3\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ4 ~ IRQ7 Interrupt Priority Control Register
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of IRQ4\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_5 : Priority of IRQ5\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_6 : Priority of IRQ6\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_7 : Priority of IRQ7\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ8 ~ IRQ11 Interrupt Priority Control Register
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority of IRQ8\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_9 : Priority of IRQ9\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_10 : Priority of IRQ10\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_11 : Priority of IRQ11\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ12 ~ IRQ15 Interrupt Priority Control Register
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of IRQ12\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_13 : Priority of IRQ13\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_14 : Priority of IRQ14\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of IRQ15\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ16 ~ IRQ19 Interrupt Priority Control Register
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_16 : Priority of IRQ16\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_17 : Priority of IRQ17\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_18 : Priority of IRQ18\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_19 : Priority of IRQ19\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ20 ~ IRQ23 Interrupt Priority Control Register
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_20 : Priority of IRQ20\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_21 : Priority of IRQ21\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_22 : Priority of IRQ22\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_23 : Priority of IRQ23\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ24 ~ IRQ27 Interrupt Priority Control Register
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_24 : Priority of IRQ24\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_25 : Priority of IRQ25\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_26 : Priority of IRQ26\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_27 : Priority of IRQ27\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ28 ~ IRQ31 Interrupt Priority Control Register
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_28 : Priority of IRQ28\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_29 : Priority of IRQ29\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_30 : Priority of IRQ30\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_31 : Priority of IRQ31\n0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Revision Number \nReads as 0x0
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Part Number of the Processor \nReads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only
PART : Architecture of the Processor \nReads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only
IMPLEMENTER : Implementer Code \n
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control State Register
address_offset : 0xD04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Contains the Active Exception Number\n
bits : 0 - 8 (9 bit)
access : read-write
Enumeration:
0 : 0
Thread mode
End of enumeration elements list.
VECTPENDING : Exception Number of the Highest Priority Pending Enabled Exception\n
bits : 12 - 20 (9 bit)
access : read-write
Enumeration:
0 : 0
No pending exceptions
End of enumeration elements list.
ISRPENDING : Interrupt Pending Flag,Excluding NMI and Faults (Read Only)\n
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#0 : 0
Interrupt not pending
#1 : 1
Interrupt pending
End of enumeration elements list.
ISRPREEMPT : Interrupt Preempt Bit(Read Only)\nIf set, a pending exception will be serviced on exit from the debug halt state
bits : 23 - 23 (1 bit)
access : read-only
PENDSTCLR : SysTick Exception Clear-pending Bit
Write Operation:
Note: This bit is write-only. When you want to clear PENDST bit, you must write 0 toPENDSTSET and write 1 to PENDSTCLR at the same time.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the SysTick exception
End of enumeration elements list.
PENDSTSET : SysTick Exception Set-pending Bit\nWrite Operation:\n
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nSysTick exception is not pending
#1 : 1
Changes SysTick exception state to pending.\nSysTick exception is pending
End of enumeration elements list.
PENDSVCLR : PendSV Clear-pending Bit
Write Operation:
This bit is write-only. To clear the PENDSV bit, you must write 0 to PENDSVSET andwrite 1 to PENDSVCLR at the same time.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Removes the pending state from the PendSV exception
End of enumeration elements list.
PENDSVSET : PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nPendSV exception is not pending
#1 : 1
Changes PendSV exception state to pending.\nPendSV exception is pending
End of enumeration elements list.
NMIPENDSET : NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception, normally the processor entersthe NMI exception handler as soon as it detects a write of 1 to this bit. Entering thehandler then clears this bit to 0. This means a read of this bit by the NMI exceptionhandler returns 1 only if the NMI signal is reasserted while the processor is executingthat handler.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect.\nNMI exception not pending
#1 : 1
Changes NMI exception state to pending.\nNMI exception pending
End of enumeration elements list.
Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Exception Active Status Clear Bit\nReserved for debug use. When writing to the register, user must write 0 to this bit, otherwise behavior is unpredictable.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : System Reset Request\nWriting this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.\nThe bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write
VECTORKEY : Register Access Key\nWrite Operation:\nWhen writing to this register, the VECTORKEY field need to be set to 0x05FA, otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of the exception status.\nRead Operation:\nRead as 0xFA05.
bits : 16 - 31 (16 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep-on-exit Enable Bit\nThis bit indicates sleep-on-exit when returning from Handler mode to Thread mode.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Do not sleep when returning to Thread mode
#1 : 1
Enter Sleep or Deep Sleep when returning from ISR to Thread mode.Setting this bit to 1 enables an interrupt driven application to avoid returning to an emptymain application
End of enumeration elements list.
SLEEPDEEP : Processor Deep Sleep and Sleep Mode Selection\nControls whether the processor uses sleep or deep sleep as its low power mode:\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Sleep mode
#1 : 1
Deep Sleep mode
End of enumeration elements list.
SEVONPEND : Send Event on Pending Bit\nWhen an event or interrupt enters pending state, the event signal wakes up the processorfrom WFE. If the processor is not waiting for an event, the event is registered and affectsthe next WFE.\nThe processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Only enabled interrupts or events can wake-up the processor, disabled interrupts areexcluded
#1 : 1
Enabled events and all interrupts, including disabled interrupts, can wake-up theprocessor
End of enumeration elements list.
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_11 : Priority of System Handler 11 - SVCall
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_14 : Priority of System Handler 14 - PendSV
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_15 : Priority of System Handler 15 - SysTick
0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
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