\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
ISP Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPEN : ISP Enable Bit (Write Protect)\nSet this bit to enable the ISP function.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP function Disabled
#1 : 1
ISP function Enabled
End of enumeration elements list.
BS : Boot Select (Write Protect)
Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Booting from APROM
#1 : 1
Booting from LDROM
End of enumeration elements list.
SPUEN : SPROM Update Enable Bit (Write Protect)\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPROM cannot be updated
#1 : 1
SPROM can be updated
End of enumeration elements list.
APUEN : APROM Update Enable Bit (Write Protect)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
APROM cannot be updated when the chip runs in APROM
#1 : 1
APROM can be updated when the chip runs in APROM
End of enumeration elements list.
CFGUEN : CONFIG Update Enable Bit (Write Protect)\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
CONFIG cannot be updated
#1 : 1
CONFIG can be updated
End of enumeration elements list.
LDUEN : LDROM Update Enable (Write Protect)\nLDROM update enable bit.\n
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
LDROM cannot be updated
#1 : 1
LDROM can be updated
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nThis bit needs to be cleared by writing 1 to it.\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0.\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection.\n(7) Erase or Program command at brown-out detected.\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands.
bits : 6 - 6 (1 bit)
access : read-write
ISP Trigger Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPGO : ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP is progressed
End of enumeration elements list.
Data Flash Base Address
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DFBA : Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1\n
bits : 0 - 31 (32 bit)
access : read-only
Flash Access Time Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOM : Frequency Optimization Mode (Write Protect)\nThe Mini58 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\n
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
#001 : 1
Frequency 24MHz
End of enumeration elements list.
ISP Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPADDR : ISP Address\nThe Mini58 series is equipped with embedded flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. and ISPADR[8:0] must be kept all 0 for Vector Page Re-map Command\nFor CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 512 bytes alignment is necessary for checksum calculation.
bits : 0 - 31 (32 bit)
access : read-write
ISP Status Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPBUSY : ISP BUSY (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
ISP operation is finished
#1 : 1
ISP operation is busy
End of enumeration elements list.
CBS : Boot Selection Of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
#00 : 0
LDROM with IAP mode
#01 : 1
LDROM without IAP mode
#10 : 2
APROM with IAP mode
#11 : 3
APROM without IAP mode
End of enumeration elements list.
ISPFF : ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:\n(1) APROM writes to itself if APUEN is set to 0.\n(2) LDROM writes to itself if LDUEN is set to 0.\n(3) CONFIG is erased/programmed if CFGUEN is set to 0.\n(4) SPROM is erased/programmed if SPUEN is set to 0.\n(5) SPROM is programmed at SPROM secured mode.\n(6) Page Erase command at LOCK mode with ICE connection.\n(7) Erase or Program command at brown-out detected.\n(8) Destination address is illegal, such as over an available range.\n(9) Invalid ISP commands.
bits : 6 - 6 (1 bit)
access : read-write
VECMAP : Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
bits : 9 - 20 (12 bit)
access : read-only
SCODE : Security Code Active Flag
This bit is set to 1 by hardware when detecting SPROM secured code is active at flash initialization, or software writes 1 to this bit to make secured code active this bit is only cleared by SPROM page erase operation.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPROM secured code is inactive
#1 : 1
SPROM secured code is active
End of enumeration elements list.
ISP Data Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.\n
bits : 0 - 31 (32 bit)
access : read-write
ISP Command Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD : ISP CMD\nISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0x00 : 0
FLASH Read
0x04 : 4
Read Unique ID
0x0b : 11
Read Company ID
0x0c : 12
Read Device ID
0x0d : 13
Read CRC32 Checksum
0x21 : 33
FLASH 32-bit Program
0x22 : 34
FLASH Page Erase
0x2d : 45
Run CRC32 Checksum Calculation
0x2e : 46
Vector Remap
End of enumeration elements list.
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