\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x300 Bytes (0x0)
size : 0x68 byte (0x0)
mem_usage : registers
protection : not protected
IRQ00 ~ IRQ31 Set-Enable Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ00 ~ IRQ31 Set-Pending Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ32 ~ IRQ63 Set-Pending Control Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ64 ~ IRQ95 Set-Pending Control Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ96 ~ IRQ101 Set-Pending Control Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Interrupt Set-pending \nThe NVIC_ISPR0-NVIC_ISPR3 registers force interrupts into the pending state, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Changes interrupt state to pending.\nInterrupt is pending
End of enumeration elements list.
IRQ00 ~ IRQ31 Clear-Pending Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ32 ~ IRQ63 Clear-Pending Control Register
address_offset : 0x184 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ64 ~ IRQ95 Clear-Pending Control Register
address_offset : 0x188 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ96 ~ IRQ101 Clear-Pending Control Register
address_offset : 0x18C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALPEND : Interrupt Clear-pending\nThe NVIC_ICPR0-NVIC_ICPR3 registers remove the pending state from interrupts, and show which interrupts are pending.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt is not pending
1 : 1
Removes pending state an interrupt.\nInterrupt is pending
End of enumeration elements list.
IRQ00 ~ IRQ31 Active Bit Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ32 ~ IRQ63 Active Bit Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ64 ~ IRQ95 Active Bit Register
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ96 ~ IRQ101 Active Bit Register
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt Active Flags\nThe NVIC_IABR0-NVIC_IABR3 registers indicate which interrupts are active.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
interrupt not active
1 : 1
interrupt active
End of enumeration elements list.
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4n_0 : Priority of IRQ_4n+0\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write
PRI_4n_1 : Priority of IRQ_4n+1\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write
PRI_4n_2 : Priority of IRQ_4n+2\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write
PRI_4n_3 : Priority of IRQ_4n+3\n'0' denotes the highest priority and '3' denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x358 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x35C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x360 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ0 ~ IRQ101 Priority Control Register
address_offset : 0x364 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ32 ~ IRQ63 Set-Enable Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ64 ~ IRQ95 Set-Enable Control Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
IRQ00 ~ IRQ31 Clear-Enable Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ32 ~ IRQ63 Clear-Enable Control Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ64 ~ IRQ95 Clear-Enable Control Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ96 ~ IRQ101 Clear-Enable Control Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALENA : Interrupt Clear Enable Bit\nThe NVIC_ICER0-NVIC_ICER3 registers disable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Disabled.\nInterrupt Enabled
End of enumeration elements list.
IRQ96 ~ IRQ101 Set-Enable Control Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Interrupt Set Enable Bit\nThe NVIC_ISER0-NVIC_ISER3 registers enable interrupts, and show which interrupts are enabled.\nWrite Operation:
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
0 : 0
No effect.\nInterrupt Disabled
1 : 1
Interrupt Enabled
End of enumeration elements list.
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