\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x10 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x54 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
USCI Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNMODE : Function Mode\nThis bit field selects the protocol for this USCI controller. Selecting a protocol that is not available or a reserved combination disables the USCI. When switching between two protocols, the USCI has to be disabled before selecting a new protocol. Simultaneously, the USCI will be reset when user write 000 to FUNMODE.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
The USCI is disabled. All protocol related state machines are set to idle state
#001 : 1
The SPI protocol is selected
#010 : 2
The UART protocol is selected
#100 : 4
The I2C protocol is selected
End of enumeration elements list.
USCI Input Data Signal Configuration Register 0
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSEL : Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized signal can be taken as input for the data shift unit
#1 : 1
The synchronized signal can be taken as input for the data shift unit
End of enumeration elements list.
ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized input signal will not be inverted
#1 : 1
The un-synchronized input signal will be inverted
End of enumeration elements list.
EDGEDET : Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode, it is suggested to set this bit field as 0x2.
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#00 : 0
The trigger event activation is disabled
#01 : 1
A rising edge activates the trigger event of input data signal
#10 : 2
A falling edge activates the trigger event of input data signal
#11 : 3
Both edges activate the trigger event of input data signal
End of enumeration elements list.
USCI Input Control Signal Configuration Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized signal can be taken as input for the data shift unit
#1 : 1
The synchronized signal can be taken as input for the data shift unit
End of enumeration elements list.
ININV : Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized input signal will not be inverted
#1 : 1
The un-synchronized input signal will be inverted
End of enumeration elements list.
USCI Input Clock Signal Configuration Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCSEL : Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The un-synchronized signal can be taken as input for the data shift unit
#1 : 1
The synchronized signal can be taken as input for the data shift unit
End of enumeration elements list.
USCI Line Control Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSB : LSB First Transmission Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first
#1 : 1
The LSB, the bit 0 of data buffer, will be transmitted/received first
End of enumeration elements list.
DATOINV : Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The value of USCIx_DAT1 is equal to the data shift register
#1 : 1
The value of USCIx_DAT1 is the inversion of data shift register
End of enumeration elements list.
CTLOINV : Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol, the control signal means nRTS signal.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
The control signal will be inverted before its output
End of enumeration elements list.
DWIDTH : Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission. The data word is always right-aligned in the data buffer. USCI support word length from 4 to 16 bits.\nNote: In UART protocol, the length can be configured as 6~13 bits.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
The data word contains 16 bits located at bit positions [15:0]
#0001 : 1
Reserved
#0010 : 2
Reserved
#0011 : 3
Reserved
#0100 : 4
The data word contains 4 bits located at bit positions [3:0]
#0101 : 5
The data word contains 5 bits located at bit positions [4:0]
#0110 : 6
The data word contains 6 bits located at bit positions [5:0]
#0111 : 7
The data word contains 7 bits located at bit positions [6:0]
#1000 : 8
The data word contains 8 bits located at bit positions [7:0]
#1001 : 9
The data word contains 9 bits located at bit positions [8:0]
#1010 : 10
The data word contains 10 bits located at bit positions [9:0]
#1011 : 11
The data word contains 11 bits located at bit positions [10:0]
#1100 : 12
The data word contains 12 bits located at bit positions [11:0]
#1101 : 13
The data word contains 13 bits located at bit positions [12:0]
#1110 : 14
The data word contains 14 bits located at bit positions [13:0]
#1111 : 15
The data word contains 15 bits located at bit positions [14:0]
End of enumeration elements list.
USCI Transmit Data Register
address_offset : 0x30 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDAT : Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission.
bits : 0 - 15 (16 bit)
access : write-only
USCI Receive Data Register
address_offset : 0x34 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDAT : Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UUART_PROTSTS[7:5]).
bits : 0 - 15 (16 bit)
access : read-only
USCI Transmit/Receive Buffer Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCLR : Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
The transmit buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
End of enumeration elements list.
RXOVIEN : Receive Buffer Overrun Error Interrupt Enable Bit
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive overrun interrupt Disabled
#1 : 1
Receive overrun interrupt Enabled
End of enumeration elements list.
RXCLR : Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
The receive buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the buffer is not taking part in data traffic
End of enumeration elements list.
TXRST : Transmit Reset\nNote: It is cleared automatically after one PCLK cycle.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the transmit-related counters, state machine, and the content of transmit shift register and data buffer
End of enumeration elements list.
RXRST : Receive Reset\nNote1: It is cleared automatically after one PCLK cycle.\nNote2: It is suggested to check the RXBUSY (UUART_PROTSTS[10]) before this bit will be set to 1.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the receive-related counters, state machine, and the content of receive shift register and data buffer
End of enumeration elements list.
USCI Transmit/Receive Buffer Status Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXEMPTY : Receive Buffer Empty Indicator (Read Only)
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer is not empty
#1 : 1
Receive buffer is empty
End of enumeration elements list.
RXFULL : Receive Buffer Full Indicator (Read Only)
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#0 : 0
Receive buffer is not full
#1 : 1
Receive buffer is full
End of enumeration elements list.
RXOVIF : Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected. If RXOVIEN (UUART_BUFCTL[14]) is enabled, the corresponding interrupt request is activated. \nNote: It is cleared by software writing 1 into this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A receive buffer overrun error event has not been detected
#1 : 1
A receive buffer overrun error event has been detected
End of enumeration elements list.
TXEMPTY : Transmit Buffer Empty Indicator (Read Only)
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit buffer is not empty
#1 : 1
Transmit buffer is empty
End of enumeration elements list.
TXFULL : Transmit Buffer Full Indicator (Read Only)
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
#0 : 0
Transmit buffer is not full
#1 : 1
Transmit buffer is full
End of enumeration elements list.
USCI Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSTIEN : Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmit start interrupt Disabled
#1 : 1
The transmit start interrupt Enabled
End of enumeration elements list.
TXENDIEN : Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmit finish interrupt Disabled
#1 : 1
The transmit finish interrupt Enabled
End of enumeration elements list.
RXSTIEN : Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receive start interrupt Disabled
#1 : 1
The receive start interrupt Enabled
End of enumeration elements list.
RXENDIEN : Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The receive end interrupt Disabled
#1 : 1
The receive end interrupt Enabled
End of enumeration elements list.
USCI PDMA Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMARST : PDMA Reset
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the USCI's PDMA control logic. This bit will be cleared to 0 automatically
End of enumeration elements list.
TXPDMAEN : PDMA Transmit Channel Available
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RXPDMAEN : PDMA Receive Channel Available
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive PDMA function Disabled
#1 : 1
Receive PDMA function Enabled
End of enumeration elements list.
PDMAEN : PDMA Mode Enable Bit
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA function Disabled
#1 : 1
PDMA function Enabled
End of enumeration elements list.
USCI Wake-up Control Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKEN : Wake-up Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled
#1 : 1
Wake-up function Enabled
End of enumeration elements list.
PDBOPT : Power Down Blocking Option
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, MCU will stop the transfer and enter Power-down mode immediately
#1 : 1
If user attempts to enter Power-down mode by executing WFI while the protocol is in transferring, the on-going transfer will not be stopped and MCU will enter idle mode immediately
End of enumeration elements list.
USCI Wake-up Status Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKF : Wake-up Flag\nWhen chip is woken up from Power-down mode, this bit is set to 1. Software can write 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-write
USCI Protocol Control Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOPB : Stop Bits\nThis bit defines the number of stop bits in an UART frame.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The number of stop bits is 1
#1 : 1
The number of stop bits is 2
End of enumeration elements list.
PARITYEN : Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The parity bit Disabled
#1 : 1
The parity bit Enabled
End of enumeration elements list.
EVENPARITY : Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Odd number of logic 1's is transmitted and checked in each word
#1 : 1
Even number of logic 1's is transmitted and checked in each word
End of enumeration elements list.
RTSAUTOEN : nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
nRTS auto-flow control Disabled
#1 : 1
nRTS auto-flow control Enabled
End of enumeration elements list.
CTSAUTOEN : nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled, the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted).
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
nCTS auto-flow control Disabled
#1 : 1
nCTS auto-flow control Enabled
End of enumeration elements list.
RTSAUDIREN : nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled, if the transmitted bytes in the TX buffer is empty, the nRTS signal is inactive automatically.\nNote 1: This bit is used for nRTS auto direction control for RS485.\nNote 2: This bit has effect only when the RTSAUTOEN is not set.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
nRTS auto direction control Disabled
#1 : 1
nRTS auto direction control Enabled
End of enumeration elements list.
ABREN : Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes, hardware will clear this bit. The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate detect function Disabled
#1 : 1
Auto-baud rate detect function Enabled
End of enumeration elements list.
DATWKEN : Data Wake-up Mode Enable Bit
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Data wake-up mode Disabled
#1 : 1
Data wake-up mode Enabled
End of enumeration elements list.
CTSWKEN : nCTS Wake-up Mode Enable Bit
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
nCTS wake-up mode Disabled
#1 : 1
nCTS wake-up mode Enabled
End of enumeration elements list.
WAKECNT : Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is woken up from Power-down mode.
bits : 11 - 14 (4 bit)
access : read-write
BRDETITV : Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN [5]) does the slave calculates the baud rate in one bits. The order of the bus shall be 1 and 0 step by step (e.g. the input data pattern shall be 0x55). The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.\nNote: This bit can be cleared to 0 by software writing '0' to the BRDETITV.
bits : 16 - 24 (9 bit)
access : read-write
STICKEN : Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stick parity Disabled
#1 : 1
Stick parity Enabled
End of enumeration elements list.
BCEN : Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit Break Control Disabled
#1 : 1
Transmit Break Control Enabled
End of enumeration elements list.
PROTEN : UART Protocol Enable Bit
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART Protocol Disabled
#1 : 1
UART Protocol Enabled
End of enumeration elements list.
USCI Protocol Interrupt Enable Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ABRIEN : Auto-baud Rate Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate interrupt Disabled
#1 : 1
Auto-baud rate interrupt Enabled
End of enumeration elements list.
RLSIEN : Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receive line status interrupt Disabled
#1 : 1
Receive line status interrupt Enabled
End of enumeration elements list.
USCI Protocol Status Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSTIF : Transmit Start Interrupt Flag\nNote 1: It is cleared by software writing one into this bit.\nNote 2: Used for user to load next transmit data when there is no data in transmit buffer.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A transmit start interrupt status has not occurred
#1 : 1
A transmit start interrupt status has occurred
End of enumeration elements list.
TXENDIF : Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
A transmit end interrupt status has not occurred
#1 : 1
A transmit end interrupt status has occurred
End of enumeration elements list.
RXSTIF : Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A receive start interrupt status has not occurred
#1 : 1
A receive start interrupt status has occurred
End of enumeration elements list.
RXENDIF : Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
A receive finish interrupt status has not occurred
#1 : 1
A receive finish interrupt status has occurred
End of enumeration elements list.
PARITYERR : Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No parity error is generated
#1 : 1
Parity error is generated
End of enumeration elements list.
FRMERR : Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is, the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No framing error is generated
#1 : 1
Framing error is generated
End of enumeration elements list.
BREAK : Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is, the total time of 'start bit' + data bits + parity + stop bits).\nNote: This bit can be cleared by writing '1' among the BREAK, FRMERR and PARITYERR bits.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Break is generated
#1 : 1
Break is generated in the receiver bus
End of enumeration elements list.
ABRDETIF : Auto-baud Rate Interrupt Flag
This bit is set when auto-baud rate detection is done among the falling edge of the input data. If the ABRIEN (UUART_PROTCTL[6]) is set, the auto-baud rate interrupt will be generated. This bit can be set 4 times when the input data pattern is 0x55 and it is cleared before the next falling edge of the input bus.
Note: This bit can be cleared by writing '1' to it.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate detect function is not done
#1 : 1
One Bit auto-baud rate detect function is done
End of enumeration elements list.
RXBUSY : RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
#0 : 0
The receiver is Idle
#1 : 1
The receiver is BUSY
End of enumeration elements list.
ABERRSTS : Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun. When the auto-baud rate counter overrun, the user shall revise the CLKDIV (UUART_BRGEN[25:16]) value and enable ABREN (UUART_PROTCTL[6]) to detect the correct baud rate again.\nNote 1: This bit is set at the same time of ABRDETIF.\nNote 2: This bit can be cleared by writing '1' to ABRDETIF or ABERRSTS.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Auto-baud rate detect counter is not overrun
#1 : 1
Auto-baud rate detect counter is overrun
End of enumeration elements list.
CTSSYNCLV : nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal.
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
#0 : 0
The internal synchronized nCTS is low
#1 : 1
The internal synchronized nCTS is high
End of enumeration elements list.
CTSLV : nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input.
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
#0 : 0
nCTS pin input is low level voltage logic state
#1 : 1
nCTS pin input is high level voltage logic state
End of enumeration elements list.
USCI Baud Rate Generator Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RCLKSEL : Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK).
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Peripheral device clock fPCLK
#1 : 1
Reserved
End of enumeration elements list.
PTCLKSEL : Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK).
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reference clock fREF_CLK
#1 : 1
fREF_CLK2 (its frequency is half of fREF_CLK)
End of enumeration elements list.
SPCLKSEL : Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
fSAMP_CLK is selected to fDIV_CLK
#01 : 1
fSAMP_CLK is selected to fPROT_CLK
#10 : 2
fSAMP_CLK is selected to fSCLK
#11 : 3
fSAMP_CLK is selected to fREF_CLK
End of enumeration elements list.
TMCNTEN : Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timing measurement counter is Disabled
#1 : 1
Timing measurement counter is Enabled
End of enumeration elements list.
TMCNTSRC : Timing Measurement Counter Clock Source Selection
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timing measurement counter with fPROT_CLK
#1 : 1
Timing measurement counter with fDIV_CLK
End of enumeration elements list.
PDSCNT : Pre-divider for Sample Counter
bits : 8 - 9 (2 bit)
access : read-write
DSCNT : Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value.
bits : 10 - 14 (5 bit)
access : read-write
CLKDIV : Clock Divider\nNote: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled. The revised value is the average bit time between bit 5 and bit 6. The user can use revised CLKDIV and new BRDETITV (UUART_PROTCTL[24:16]) to calculate the precise baud rate.
bits : 16 - 25 (10 bit)
access : read-write
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