SYST_CTL

NVIC_ISER

SYST_RVR

SYST_CVR

NVIC_ICER

NVIC_ISPR

NVIC_ICPR

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

CPUID

ICSR

AIRCR

SCR

SHPR2

SHPR3

ENABLE : None
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICKINT : None
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLKSRC : None
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

COUNTFLAG : Returns 1 If Timer Counted To 0 Since Last Time This Register Was Read\n COUNTFLAG is set by a count transition from 1 to 0.\n COUNTFLAG is cleared on read or by a write to the Current Value register.
bits : 16 - 16 (1 bit)
access : read-write

SETENA : Enable one or more interrupts within a group of 32. Each Bit Represents An Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47) \nWriting 1 will enable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

RELOAD : The value to load into the Current Value register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write

CURRENT : Current Counter Value \nThis is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the register to 0. Unsupported bits RAZ (Read As Zero, writes ignore) (See SysTick Reload Value register).
bits : 0 - 23 (24 bit)
access : read-write

CLRENA : Disable one or more interrupts within a group of 32. Each Bit Represents An Interrupt Number From IRQ0 ~ IRQ31 (Vector Number From 16 ~ 47) \nWriting 1 will disable the associated interrupt.\nWriting 0 has no effect.\nThe register reads back with the current enable state.
bits : 0 - 31 (32 bit)
access : read-write

SETPEND : Writing 1 To A Bit To Set Pending State Of The Associated Interrupt Under Software Control Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

CLRPEND : Writing 1 To A Bit To Remove The Pending State Of Associated Interrupt Under Software Control Each bit represents an interrupt number from IRQ0 ~ IRQ31 (Vector number from 16 ~ 47).\nWriting 0 has no effect.\nThe register reads back with the current pending state.
bits : 0 - 31 (32 bit)
access : read-write

PRI_0 : Priority Of IRQ0 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_1 : Priority Of IRQ1 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_2 : Priority Of IRQ2 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_3 : Priority Of IRQ3 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_4 : Priority Of IRQ4 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_5 : Priority Of IRQ5 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_6 : Priority Of IRQ6 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_7 : Priority Of IRQ7 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_8 : Priority Of IRQ8 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_9 : Priority Of IRQ9 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_10 : Priority Of IRQ10 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_11 : Priority Of IRQ11 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_12 : Priority Of IRQ12 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_13 : Priority Of IRQ13 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_14 : Priority Of IRQ14 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority Of IRQ15 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_16 : Priority Of IRQ16 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_17 : Priority Of IRQ17 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_18 : Priority Of IRQ18 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_19 : Priority Of IRQ19 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_20 : Priority Of IRQ20 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_21 : Priority Of IRQ21 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_22 : Priority Of IRQ22 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_23 : Priority Of IRQ23 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_24 : Priority Of IRQ24 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_25 : Priority Of IRQ25 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_26 : Priority Of IRQ26 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_27 : Priority Of IRQ27 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_28 : Priority Of IRQ28 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 6 - 7 (2 bit)
access : read-write

PRI_29 : Priority Of IRQ29 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 14 - 15 (2 bit)
access : read-write

PRI_30 : Priority Of IRQ30 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_31 : Priority Of IRQ31 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

REVISION : Reads as 0x0
bits : 0 - 3 (4 bit)
access : read-only

PARTNO : Reads as 0xC20.
bits : 4 - 15 (12 bit)
access : read-only

PART : Reads as 0xC for ARMv6-M parts
bits : 16 - 19 (4 bit)
access : read-only

IMPLEMENTER : None
bits : 24 - 31 (8 bit)
access : read-only

VECTACTIVE : If value of VECTACTIVE 1: the exception number for the current executing exception.
bits : 0 - 8 (9 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECTPENDING : Indicates The Exception Number For The Highest Priority Pending Exception\nThe pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier. A value of zero indicates no pending exceptions.
bits : 12 - 20 (9 bit)
access : read-write

ISRPENDING : Indicates if an external configurable (NVIC generated) interrupt is pending.
bits : 22 - 22 (1 bit)
access : read-write

ISRPREEMPT : If set, a pending exception will be serviced on exit from the debug halt state.
bits : 23 - 23 (1 bit)
access : read-write

PENDSTCLR : Write 1 to clear a pending SysTick.
bits : 25 - 25 (1 bit)
access : read-write

PENDSTSET : Set A Pending SysTick Reads back with current state (1 if Pending, 0 if not).
bits : 26 - 26 (1 bit)
access : read-write

PENDSVCLR : Write 1 to clear a pending PendSV interrupt.
bits : 27 - 27 (1 bit)
access : read-write

PENDSVSET : Set A Pending PendSV Interrupt\nThis is normally used to request a context switch. Reads back with current state (1 if Pending, 0 if not).
bits : 28 - 28 (1 bit)
access : read-write

NMIPENDSET : Setting This Bit Will Activate An NMI\nSince NMI is the highest priority exception, it will activate as soon as it is registered. Reads back with current state (1 if Pending, 0 if not).
bits : 31 - 31 (1 bit)
access : read-write

VECTCLRACTIVE : Set This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThe bit is a write only bit and can only be written when the core is halted.\nNote: It is the debugger's responsibility to re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write

SYSRESETREQ : Writing This Bit 1 Will Cause A Reset Signal To Be Asserted To The Chip To Indicate A Reset Is Requested\nThe bit is a write only bit and self-clears as part of the reset sequence.
bits : 2 - 2 (1 bit)
access : read-write

VECTORKEY : When write this register, this field should be 0x05FA, otherwise the write action will be unpredictable.
bits : 16 - 31 (16 bit)
access : read-write

SLEEPONEXIT : When Set To 1, The Core Can Enter A Sleep State On An Exception Return To Thread Mode This is the mode and exception level entered at reset, the base level of execution.
bits : 1 - 1 (1 bit)
access : read-write

SLEEPDEEP : A qualifying hint that indicates waking from sleep might take longer.
bits : 2 - 2 (1 bit)
access : read-write

SEVONPEND : When enabled, interrupt transitions from Inactive to Pending are included in the list of wake-up events for the WFE instruction.
bits : 4 - 4 (1 bit)
access : read-write

PRI_11 : Priority Of System Handler 11 - SVCall 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write

PRI_14 : Priority Of System Handler 14 - PendSV 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 22 - 23 (2 bit)
access : read-write

PRI_15 : Priority Of System Handler 15 - SysTick 0 denotes the highest priority and 3 denotes the lowest priority.
bits : 30 - 31 (2 bit)
access : read-write