PDID

CPR

RegLockAddr

TEMPCTL

PA_L_MFP

PA_H_MFP

PB_L_MFP

PB_H_MFP

RST_SRC

PC_L_MFP

PC_H_MFP

PD_L_MFP

PD_H_MFP

PE_L_MFP

PE_H_MFP

PF_L_MFP

PORCTL

BODCTL

BODSTS

VREFCTL

IPRST_CTL1

IRCTRIMCTL

IRCTRIMIEN

IRCTRIMINT

IPRST_CTL2

PDID : Part Device ID \nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only

HPE : High Performance Enable\nThis bit is used to control chip operation performance.\nWhen this bit set, internal RAM and GPIO access is working with zero wait state, Flash controller will predict next address more efficiently \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RegUnLock : None
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VTEMP_EN : Temperature Sensor Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PA0_MFP : PA.0 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PA1_MFP : PA.1 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PA2_MFP : PA.2 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PA3_MFP : PA.3 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PA4_MFP : PA.4 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PA5_MFP : PA.5 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PA6_MFP : PA.6 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PA7_MFP : PA.7 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PA8_MFP : PA.8 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PA9_MFP : PA.9 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PA10_MFP : PA.10 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PA11_MFP : PA.11 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PA12_MFP : PA.12 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PA13_MFP : PA.13 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PA14_MFP : PA.14 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PA15_MFP : PA.15 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PB0_MFP : PB.0 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PB1_MFP : PB.1 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PB2_MFP : PB.2 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PB3_MFP : PB.3 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PB4_MFP : PB.4 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PB5_MFP : PB.5 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PB6_MFP : PB.6 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PB7_MFP : PB.7 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PB8_MFP : PB.8 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PB9_MFP : PB.9 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PB10_MFP : PB.10 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PB11_MFP : PB.11 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PB12_MFP : PB.12 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PB13_MFP : PB.13 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PB14_MFP : PB.14 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PB15_MFP : PB.15 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

RSTS_POR : The RSTS_POR Flag Is Set By The Reset Signal From The Power-On Reset (POR) Module Or Bit CHIP_RST (IPRST_CTL1[0]) To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_PAD : The RSTS_PAD Flag Is Set By The Reset Signal From The /RESET Pin To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_WDT : The RSTS_WDT Flag Is Set By The Reset Signal From The Watch-Dog Timer Module To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_BOD : The RSTS_BOD Flag Is Set By The Reset Signal From The Brown-Out-Detected Module To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_SYS : The RSTS_SYS Flag Is Set By The Reset Signal From The Cortex_M0 Kernel To Indicate The Previous Reset Source This bit is cleared by writing 1 to itself.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RSTS_CPU : The RSTS_CPU Flag Is Set By Hardware If Software Writes CPU_RST (IPRST_CTL1[1]) 1 To Rest Cortex-M0 CPU Kernel And Flash Memory Controller (FMC) This bit is cleared by writing 1 to itself.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PC0_MFP : PC.0 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PC1_MFP : PC.1 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PC2_MFP : PC.2 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PC3_MFP : PC.3 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PC4_MFP : PC.4 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PC5_MFP : PC.5 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PC6_MFP : PC.6 Pin Function Selection\n\n
bits : 24 - 26 (3 bit)
access : read-write

PC7_MFP : PC.7 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PC8_MFP : PC.8 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PC9_MFP : PC.9 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PC10_MFP : PC.10 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PC11_MFP : PC.11 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PC12_MFP : PC.12 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PC13_MFP : PC.13 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PC14_MFP : PC.14 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PC15_MFP : PC.15 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PD0_MFP : PD.0 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PD1_MFP : PD.1 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PD2_MFP : PD.2 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PD3_MFP : PD.3 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PD4_MFP : PD.4 Pin Function Selection\n\n
bits : 16 - 18 (3 bit)
access : read-write

PD5_MFP : PD.5 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PD6_MFP : PD.6 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PD7_MFP : PD.7 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PD8_MFP : PD.8 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PD9_MFP : PD.9 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PD10_MFP : PD.10 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PD11_MFP : PD.11 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PD12_MFP : PD.12 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PD13_MFP : PD.13 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PD14_MFP : PD.14 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PD15_MFP : PD.15 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PE0_MFP : PE.0 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PE1_MFP : PE.1 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PE2_MFP : PE.2 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PE3_MFP : PE.3 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PE4_MFP : PE.4 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PE5_MFP : PE.5 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PE6_MFP : PE.6 Pin Function Selection\nAll setting : GPIOE[6]
bits : 24 - 26 (3 bit)
access : read-write

PE7_MFP : PE.7 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PE8_MFP : PE.8 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PE9_MFP : PE.9 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PE10_MFP : PE.10 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PE11_MFP : PE.11 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PE12_MFP : PE.12 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PE13_MFP : PE.13 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

PE14_MFP : PE.14 Pin Function Selection\n
bits : 24 - 26 (3 bit)
access : read-write

PE15_MFP : PE.15 Pin Function Selection\n
bits : 28 - 30 (3 bit)
access : read-write

PF0_MFP : PF.0 Pin Function Selection\n
bits : 0 - 2 (3 bit)
access : read-write

PF1_MFP : PF.1 Pin Function Selection\n
bits : 4 - 6 (3 bit)
access : read-write

PF2_MFP : PF.2 Pin Function Selection\n
bits : 8 - 10 (3 bit)
access : read-write

PF3_MFP : PF.3 Pin Function Selection\n
bits : 12 - 14 (3 bit)
access : read-write

PF4_MFP : PF.4 Pin Function Selection\n
bits : 16 - 18 (3 bit)
access : read-write

PF5_MFP : PF.5 Pin Function Selection\n
bits : 20 - 22 (3 bit)
access : read-write

POR_DIS_CODE : Power-On Reset Enable Control\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. If setting the POR_DIS_CODE to 0x5AA5, the POR reset function will be disabled and the POR function will be active again when POR_DIS_CODE is set to another value or POR_DIS_CODE is reset by chip other reset functions, including: /RESET, Watchdog Timer reset, BOD reset, ICE reset command and the software-chip reset function
bits : 0 - 15 (16 bit)
access : read-write

BOD17_EN : Brown-Out Detector 1.7V Function Enable \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD20_EN : Brown-Out Detector 2.0 V Function Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nBOD20_EN is default on. If SW disables it, Brown-out Detector 2.0 V function is not disabled until chip enters power-down mode. If system is not in power-down mode, BOD20_EN will be enabled by hardware automatically.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD25_EN : Brown-Out Detector 2.5 V Function Enable \nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD17_RST_EN : BOD 1.7 V Reset Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD20_RST_EN : BOD 2.0 V Reset Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19]
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD25_RST_EN : BOD 2.5 V Reset Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nThe default value is set by flash controller user configuration register config0 bit[20:19]
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD17_INT_EN : BOD 1.7 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD20_INT_EN : BOD 2.0 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD25_INT_EN : BOD 2.5 V Interrupt Enable\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BOD_INT : Brown-Out Detector Interrupt Status\nThis bit is cleared by writing 1 to itself.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BOD17_OUT : Brown-Out Detector Output Status\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BOD20_OUT : Brown-Out Detector Output Status\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BOD25_OUT : Brown-Out Detector Output Status\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BGP_EN : Band-Gap Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5V or 2.5V reference voltage.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REG_EN : Regulator Enable\nEnable internal 1.5V or 2.5V reference voltage.\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SEL25 : Regulator Output Voltage Selection\nSelect internal reference voltage level.\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXT_MODE : Regulator External Mode\nThis is a protected register. Please refer to open lock sequence to program it.\nUsers can output regulator output voltage in Vref pin if EXT_MODE is high.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHIP_RST : CHIP One Shot Reset This is a protected register. Please refer to open lock sequence to program it. Setting this bit will reset the whole chip, including CPU kernel and all peripherals like power-on reset and this bit will automatically return to 0 after the 2 clock cycles. The chip setting from flash will be also reloaded when chip one shot reset. Note: In the following condition, chip setting from flash will be reloaded The Power-On Reset Brown-Out-Detected Reset The low level on the /RESET pin Set CHIP_RST(IPRST_CTL1[0])
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_RST : CPU Kernel One Shot Reset This is a protected register. Please refer to open lock sequence to program it. Setting this bit will only reset the CPU kernel and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_RST : DMA Controller Reset This is a protected register. Please refer to open lock sequence to program it. Set this bit 1 will generate a reset signal to the DMA. SW needs to set this bit to low to release reset signal.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EBI_RST : EBI Controller Reset This is a protected register. Please refer to open lock sequence to program it. Set this bit 1 will generate a reset signal to the EBI. SW needs to set this bit to low to release reset signal.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIM_SEL : Trim Frequency Selection\n
bits : 0 - 1 (2 bit)
access : read-write

TRIM_LOOP : Trim Calculation Loop\n
bits : 4 - 5 (2 bit)
access : read-write

TRIM_RETRY_CNT : Trim Value Update Limitation Count\n
bits : 6 - 7 (2 bit)
access : read-write

TRIM_FAIL_IEN : Trim Failure Interrupt Enable\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by TRIM_SEL (IRCTRIMCTL[1:0]).\nIf this bit is high and TRIM_FAIL_INT (IRCTRIMINT[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

_32K_ERR_IEN : 32.768 KHz Clock Error Interrupt Enable\nThis bit controls if CPU would get an interrupt while 32.768 kHz clock is inaccuracy during auto trim operation.\nIf this bit is high, and 32K_ERR_INT (IRCTRIMINT[2]) is set during auto trim operation, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FREQ_LOCK : HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency lock.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write

TRIM_FAIL_INT : Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and HIRC clock frequency still doesn't lock. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TRIM_FAIL_IEN (IRCTRIMIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. Write 1 to clear this to zero.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

_32K_ERR_INT : 32.768 KHz Clock Error Interrupt Status\nThis bit indicates that 32.768 kHz clock frequency is inaccuracy. Once this bit is set, the auto trim operation stopped and TRIM_SEL (IRCTRIMCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and 32K_ERR_IEN (IRCTRIMIEN[2]) is high, an interrupt will be triggered to notify the 32.768 kHz clock frequency is inaccuracy. Write 1 to clear this to zero.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO_RST : GPIO Controller Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_RST : Timer0 Controller Reset\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_RST : Timer1 Controller Reset\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_RST : Timer2 Controller Reset\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3_RST : Timer3 Controller Reset\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_RST : I2C0 Controller Reset\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1_RST : I2C1 Controller Reset\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_RST : SPI0 Controller Reset\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_RST : SPI1 Controller Reset\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2_RST : SPI2 Controller Reset\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_RST : UART0 Controller Reset\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_RST : UART1 Controller Reset\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0_RST : PWM0 Controller Reset\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1_RST : PWM1 Controller Reset\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBD_RST : USB Device Controller Reset\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_RST : ADC Controller Reset\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_RST : I2S Controller Reset\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC0_RST : SC 0 Controller Reset\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC1_RST : SC 1 Controller Reset\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.