PWRCTL

CLKSEL0

CLKSEL1

CLKSEL2

CLKDIV0

CLKDIV1

PLLCTL

FRQDIV

PD_WK_IS

AHBCLK

APBCLK

CLKSTATUS

HXT_EN : HXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nThe bit default value is set by flash controller user configuration register config0 [26]. \nHXT is disabled by default.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXT_EN : LXT Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLXT is disabled by default.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HIRC_EN : HIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nHIRC is enabled by default.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIRC_EN : LIRC Control\nThis is a protected register. Please refer to open lock sequence to program it.\nLIRC is enabled by default.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WK_DLY : Wake-Up Delay Counter Enable\nThis is a protected register. Please refer to open lock sequence to program it.\nWhen chip wakes up from Power-down mode, the clock control will delay 4096 clock cycles to wait HXT stable or 16 clock cycles to wait HIRC stable.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_WK_IE : Power-Down Mode Wake-Up Interrupt Enable \nThis is a protected register. Please refer to open lock sequence to program it.\nPD_WK_INT will be set if both PD_WK_IS (PD_WK_IS[0]) and PD_WK_IE (PWRCTL[5]) are high.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_EN : Chip Power-Down Mode Enable Bit This is a protected register. Please refer to open lock sequence to program it. When CPU sets this bit, the chip power down is enabled and chip will not enter Power-down mode until CPU sleep mode is also active. When chip wakes up from Power-down mode, this bit will be auto cleared. When chip is in Power-down mode, the LDO, HXT and HIRC will be disabled, but LXT and LIRC are not controlled by Power-down mode. When power down, the PLL and system clock (CPU, HCLKx and PCLKx) are also disabled no matter the Clock Source selection. Peripheral clocks are not controlled by this bit, if peripheral Clock Source is from LXT or LIRC. In Power-down mode, flash macro power is ON. NOTE: It inhibits to set both PD_EN and DPD_EN high.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_SELXT : HXT SELXT\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_GAIN : HXT Gain Control Bit\nThis is a protected register. Please refer to open lock sequence to program it.\nGain control is used to enlarge the gain of crystal to make sure crystal wok normally. If gain control is enabled, crystal will consume more power than gain control off. \n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LXT_SCNT : LXT Stable Time Control\nThis is a protected register. Please refer to open lock sequence to program it.\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HCLK_S : HCLK Clock Source Selection\n
bits : 0 - 2 (3 bit)
access : read-write

UART_S : UART 0/1 Clock Source Selection (UART0 And UART1 Use The Same Clock Source Selection)\n
bits : 0 - 1 (2 bit)
access : read-write

ADC_S : ADC Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

PWM0_CH01_S : PWM0 Channel 0 And Channel 1 Clock Source Selection\n
bits : 4 - 5 (2 bit)
access : read-write

PWM0_CH23_S : PWM0 Channel 2 And Channel 3 Clock Source Selection\n
bits : 6 - 7 (2 bit)
access : read-write

TMR0_S : TIMER 0 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

TMR1_S : TIMER 1 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

FRQDIV_S : Clock Divider Clock Source Selection\n
bits : 2 - 3 (2 bit)
access : read-write

PWM1_CH01_S : PWM1 Channel 0 And Channel 1 Clock Source Selection\n
bits : 4 - 5 (2 bit)
access : read-write

PWM1_CH23_S : PWM1 Channel 2 And Channel 2 Clock Source Selection\n
bits : 6 - 7 (2 bit)
access : read-write

TMR2_S : TIMER 2 Clock Source Selection\n
bits : 8 - 10 (3 bit)
access : read-write

TMR3_S : TIMER 3 Clock Source Selection\n
bits : 12 - 14 (3 bit)
access : read-write

I2S_S : I2S Clock Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write

SC_S : SC Clock Source Selection\n
bits : 18 - 19 (2 bit)
access : read-write

HCLK_N : HCLK Clock Divide Number From HCLK Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

USB_N : USB Clock Divide Number From PLL Clock \n
bits : 4 - 7 (4 bit)
access : read-write

UART_N : UART Clock Divide Number From UART Clock Source\n
bits : 8 - 11 (4 bit)
access : read-write

I2S_N : I2S Clock Divide Number From I2S Clock Source\n
bits : 12 - 15 (4 bit)
access : read-write

ADC_N : ADC Clock Divide Number From ADC Clock Source\n
bits : 16 - 23 (8 bit)
access : read-write

SC0_N : SC 0 Clock Divide Number From SC 0 Clock Source\n
bits : 28 - 31 (4 bit)
access : read-write

SC1_N : SC 1 Clock Divide Number From SC 1 Clock Source\n
bits : 0 - 3 (4 bit)
access : read-write

FB_DV : PLL Feedback Divider Control Pins \nRefer to the formulas below the table.\nThe range of FB_DV is from 0 to 63.
bits : 0 - 4 (5 bit)
access : read-write

IN_DV : PLL Input Divider Control Pins\nRefer to the formulas below the table.
bits : 8 - 9 (2 bit)
access : read-write

OUT_DV : PLL Output Divider Control Pins \nRefer to the formulas below the table.
bits : 12 - 12 (1 bit)
access : read-write

PD : Power-Down Mode If set the PD_EN(PWRCTL[6]) 1 , the PLL will enter Power-down mode too
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PLL_SRC : PLL Source Clock Select\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FSEL : Divider Output Frequency Selection Bits\nThe formula of output frequency is\nWhere Fin is the input clock frequency, Fout is the frequency of divider output clock and N is the 4-bit value of FSEL(FRQDIV[3:0]).
bits : 0 - 3 (4 bit)
access : read-write

FDIV_EN : Frequency Divider Enable Bit\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PD_WK_IS : Wake-Up Interrupt Sstatus In Chip Power-Down Mode\nThis bit indicates that some event resumes chip from Power-down mode \nThe status is set if external interrupts, UART, GPIO, RTC, USB, SPI, Timer, WDT, and BOD wake-up occurred.\nWrite 1 to clear this bit.
bits : 0 - 0 (1 bit)
access : read-only

GPIO_EN : GPIO Controller Clock Enable \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_EN : DMA Controller Clock Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISP_EN : Flash ISP Controller Clock Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EBI_EN : EBI Controller Clock Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SRAM_EN : SRAM Controller Clock Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TICK_EN : System Tick Clock Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDT_EN : Watch-Dog Timer Clock Enable Control \nThis is a protected register. Please refer to open lock sequence to program it.\nThis bit is used to control the WDT APB clock only, The WDT engine Clock Source is from LIRC.\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTC_EN : Real-Time-Clock Clock Enable Control \nThis bit is used to control the RTC APB clock only, The RTC engine Clock Source is from LXT.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR0_EN : Timer0 Clock Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR1_EN : Timer1 Clock Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR2_EN : Timer2 Clock Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR3_EN : Timer3 Clock Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FDIV_EN : Frequency Divider Output Clock Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C0_EN : I2C0 Clock Enable Control \n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2C1_EN : I2C1 Clock Enable Control \n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI0_EN : SPI0 Clock Enable Control \n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI1_EN : SPI1 Clock Enable Control \n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPI2_EN : SPI2 Clock Enable Control \n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART0_EN : UART0 Clock Enable Control\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

UART1_EN : UART1 Clock Enable Control\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0_CH01_EN : PWM0 Channel 0 And Channel 1Clock Enable Control\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM0_CH23_EN : PWM0 Channel 2 And Channel 3 Clock Enable Control\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1_CH01_EN : PWM1 Channel 0 And Channel 1 Clock Enable Control\n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PWM1_CH23_EN : PWM1 Channel 2 And Channel 3 Clock Enable Control\n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

USBD_EN : USB FS Device Controller Clock Enable Control\n
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADC_EN : Analog-Digital-Converter (ADC) Clock Enable Control\n
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2S_EN : I2S Clock Enable Control\n
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC0_EN : SmartCard 0 Clock Enable Control\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SC1_EN : SmartCard 1 Clock Enable Control\n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

HXT_STB : HEXT Clock Source Stable Flag\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LXT_STB : LEXT Clock Source Stable Flag\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PLL_STB : PLL Clock Source Stable Flag\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIRC_STB : LIRC Clock Source Stable Flag\n
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

HIRC_STB : HIRC Clock Source Stable Flag\n
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLK_SW_FAIL : Clock Switch Fail Flag\nThis bit will be set when target switch Clock Source is not stable. This bit is write 1 clear
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.