\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
External Bus Interface General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExtEN : EBI Enable Control\nThis bit is the functional enable bit for EBI.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function is disabled
#1 : 1
EBI function is enabled
End of enumeration elements list.
ExtBW16 : EBI Data Width 16-Bit\nThis bit defines if the data bus is 8-bit or 16-bit.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
MCLKDIV : External Output Clock Divider\nThe frequency of EBI output clock is controlled by MCLKDIV as shown in the following table.\n
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : 0
HCLK/1
0x1 : 1
HCLK/2
0x2 : 2
HCLK/4
0x3 : 3
HCLK/8
0x4 : 4
HCLK/16
0x5 : 5
HCLK/32
0x6 : 6
HCLK/1
0x7 : 7
HCLK/1
End of enumeration elements list.
MCLKEN : External Clock Enable Control\nThis bit control if EBI generates the clock to external device.\nIf external device is a synchronous device, it's necessary to set this bit high to enable EBI generating clock to external device.\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#1 : 1
Enabled EBI to generate clock to external device
End of enumeration elements list.
ExttALE : Expand Time Of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.\n
bits : 16 - 18 (3 bit)
access : read-write
External Bus Interface Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExttACC : EBI Data Access Time\nExttACC define data access time (tACC).\n
bits : 0 - 4 (5 bit)
access : read-write
ExttAHD : EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).\n
bits : 8 - 10 (3 bit)
access : read-write
ExtIW2X : Idle State Cycle After Write\nWhen write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.\n
bits : 12 - 15 (4 bit)
access : read-write
ExtIR2W : Idle State Cycle Between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS return to high if ExtIR2W is not zero.\n
bits : 16 - 19 (4 bit)
access : read-write
ExtIR2R : Idle State Cycle Between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.\n
bits : 24 - 27 (4 bit)
access : read-write
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