GPIOA_PMD

GPIOA_PIN

GPIOE_PMD

GPIOE_OFFD

GPIOE_DOUT

GPIOE_DMASK

GPIOE_PIN

GPIOE_DBEN

GPIOE_IMD

GPIOE_IER

GPIOE_ISRC

GPIOE_PUEN

GPIOA_DBEN

GPIOF_PMD

GPIOF_OFFD

GPIOF_DOUT

GPIOF_DMASK

GPIOF_PIN

GPIOF_DBEN

GPIOF_IMD

GPIOF_IER

GPIOF_ISRC

GPIOF_PUEN

GPIOA_IMD

DBNCECON

GPIOA_IER

GPIOA_ISRC

GPIOA0

GPIOA1

GPIOA2

GPIOA3

GPIOA4

GPIOA5

GPIOA6

GPIOA7

GPIOA8

GPIOA9

GPIOA10

GPIOA11

GPIOA12

GPIOA13

GPIOA14

GPIOA15

GPIOA_PUEN

GPIOB0

GPIOB1

GPIOB2

GPIOB3

GPIOB4

GPIOB5

GPIOB6

GPIOB7

GPIOB8

GPIOB9

GPIOB10

GPIOB11

GPIOB12

GPIOB13

GPIOB14

GPIOB15

GPIOC0

GPIOC1

GPIOC2

GPIOC3

GPIOC4

GPIOC5

GPIOC6

GPIOC7

GPIOC8

GPIOC9

GPIOC10

GPIOC11

GPIOC12

GPIOC13

GPIOC14

GPIOC15

GPIOD0

GPIOD1

GPIOD2

GPIOD3

GPIOD4

GPIOD5

GPIOD6

GPIOD7

GPIOD8

GPIOD9

GPIOD10

GPIOD11

GPIOD12

GPIOD13

GPIOD14

GPIOD15

GPIOE0

GPIOE1

GPIOE2

GPIOE3

GPIOE4

GPIOE5

GPIOE6

GPIOE7

GPIOE8

GPIOE9

GPIOE10

GPIOE11

GPIOE12

GPIOE13

GPIOE14

GPIOE15

GPIOF0

GPIOF1

GPIOF2

GPIOF3

GPIOF4

GPIOF5

GPIOA_OFFD

GPIOB_PMD

GPIOB_OFFD

GPIOB_DOUT

GPIOB_DMASK

GPIOB_PIN

GPIOB_DBEN

GPIOB_IMD

GPIOB_IER

GPIOB_ISRC

GPIOB_PUEN

GPIOA_DOUT

GPIOC_PMD

GPIOC_OFFD

GPIOC_DOUT

GPIOC_DMASK

GPIOC_PIN

GPIOC_DBEN

GPIOC_IMD

GPIOC_IER

GPIOC_ISRC

GPIOC_PUEN

GPIOA_DMASK

GPIOD_PMD

GPIOD_OFFD

GPIOD_DOUT

GPIOD_DMASK

GPIOD_PIN

GPIOD_DBEN

GPIOD_IMD

GPIOD_IER

GPIOD_ISRC

GPIOD_PUEN

PMD0 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD1 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD2 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD3 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD4 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD5 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD6 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD7 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD8 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD9 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 18 - 19 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD10 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD11 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 22 - 23 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD12 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD13 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 26 - 27 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD14 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PMD15 : GPIO Port [X] Pin [N] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: \nFor GPIOC_PMD, PMD4~PMD5 and PMD12~PMD13 are reserved.\nFor GPIOD_PMD, PMD0~PMD5 and PMD8~PMD13 are reserved.\nFor GPIOE_PMD, PMD0~PMD4 and PMD6~PMD15 are reserved.\nFor GPIOF_PMD, PMD2 ~ PMD15 are reserved.
bits : 30 - 31 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PIN0 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : GPIO Port [X] Pin [N] Value\nThe value read from each of these bit reflects the actual status of the respective GPIO pin\nNote: \nFor GPIOC_PIN, bits [5:4] and [13:12] are reserved.\nFor GPIOD_PIN, bits [5:0] and [13:8] are reserved.\nFor GPIOE_PIN, bits [4:0] and [15:6] are reserved.\nFor GPIOF_PIN, bits [15:2] are reserved.
bits : 15 - 15 (1 bit)
access : read-only

DBEN0 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN1 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN2 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN3 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN4 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN5 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN6 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN7 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN8 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN9 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN10 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN11 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN12 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN13 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN14 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBEN15 : GPIO Port [X] Pin [N] Input Signal De-Bounce Enable DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt. DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored. Note: For GPIOC_DBEN, bits [5:4] and [13:12] are reserved. For GPIOD_DBEN, bits [5:0] and [13:8] are reserved. For GPIOE_DBEN, bits [4:0] and [15:6] are reserved. For GPIOF_DBEN, bits [15:2] are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD0 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD1 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD2 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD3 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD4 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD5 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD6 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD7 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD8 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD9 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD10 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD11 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD12 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD13 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD14 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

IMD15 : GPIO Port [X] Pin [N] Edge Or Level Detection Interrupt Control\nIMD[n] used to decide whether the interrupt is controlled by level trigger or by edge trigger. If the interrupt is controlled by edge trigger, the trigger source is sampled by de-bounce. If the interrupt is controlled by level trigger, the input source is sampled by one clock and the interrupt generates. \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: \nFor GPIOC_IMD, bits [5:4] and [13:12] are reserved.\nFor GPIOD_IMD, bits [5:0] and [13:8] are reserved.\nFor GPIOE_IMD, bits [4:0] and [15:6] are reserved.\nFor GPIOF_IMD, bits [15:2] are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLKSEL : De-Bounce Sampling Cycle Selection\n
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLKSRC : De-Bounce Counter Clock Source Selection\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBCLK_ON : De-Bounce Clock Enable\nThis bit controls if the de-bounce clock is enabled.\nHowever, if GPIO pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER0 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER1 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER2 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER3 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER4 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER5 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER6 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER7 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER8 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER9 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER10 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER11 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER12 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER13 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER14 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FIER15 : GPIO Port [X] Pin [N] Interrupt Enable By Input Falling Edge Or Input Level Low FIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function When set the FIER[n] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt. Note: For GPIOC_IER, bits [5:4] and [13:12] are reserved. For GPIOD_IER, bits [5:0] and [13:8] are reserved. For GPIOE_IER, bits [4:0] and [15:6] are reserved. For GPIOF_IER, bits [15:2] are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER0 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER1 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER2 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER3 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER4 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER5 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER6 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER7 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER8 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER9 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER10 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER11 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER12 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER13 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER14 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RIER15 : GPIO Port [X] Pin [N] Interrupt Enable By Input Rising Edge Or Input Level High RIER[n] is used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function When set the RIER[x] bit 1 : If the interrupt is level mode trigger, the input PIN[n] state at level high will generate the interrupt. If the interrupt is edge mode trigger, the input PIN[n] state change from low-to-high will generate the interrupt. Note: For GPIOC_IER, bits [21:20] and [29:28] are reserved. For GPIOD_IER, bits [21:16] and [29:24] are reserved. For GPIOE_IER, bits [20:16] and [31:22] are reserved. For GPIOF_IER, bits [31:18] are reserved.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC0 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC1 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC2 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC3 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC4 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC5 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC6 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC7 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC8 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC9 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC10 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC11 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC12 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC13 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC14 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISRC15 : GPIO Port [X] Pin [N] Interrupt Trigger Source Indicator\nRead :\nNote: \nFor GPIOC_ISRC, bits [5:4] and [13:12] are reserved.\nFor GPIOD_ISRC, bits [5:0] and [13:8] are reserved.\nFor GPIOE_ISRC, bits [4:0] and [15:6] are reserved.\nFor GPIOF_ISRC, bits [15:2] are reserved.
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

GPIO : GPIO Port [X] Pin [N] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port [x] pin [n] value.\nRead:\nNote: The write operation will not be affected by register GPIOx_DMASK.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.