VDMA_CSR (CSR)

VDMA_CSAR (CSAR)

VDMA_CDAR (CDAR)

VDMA_CBCR (CBCR)

VDMA_IER (IER)

VDMA_ISR (ISR)

VDMA_SASOCR (SASOCR)

VDMA_DASOCR (DASOCR)

VDMA_SAR (SAR)

VDMA_DAR (DAR)

VDMA_BUF0 (BUF0)

VDMA_BUF1 (BUF1)

VDMA_BCR (BCR)

VDMACEN : VDMA Channel Enable Control Setting this bit to 1 enables VDMA's operation. If this bit is cleared, VDMA will ignore all VDMA request and force Bus Master into IDLE state. Note: SW_RST will clear this bit.
bits : 0 - 0 (1 bit)
access : read-write

SW_RST : Software Engine Reset\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

STRIDE_EN : Stride Mode Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DIR_SEL : Transfer Source/Destination Address Direction Selection\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIG_EN : Trigger Enable Control\nNote: When VDMA transfer is completed, this bit will be cleared automatically.\nIf the bus error occurs, all VDMA transfer will be stopped. User must reset all VDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VDMA_CSAR : VDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the VDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_CDAR : VDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the VDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_CBCR : VDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of VDMA.
bits : 0 - 15 (16 bit)
access : read-only

TABORT_IE : VDMA Read/Write Target Abort Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TD_IE : VDMA Transfer Done Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TABORT_IS : VDMA Read/Write Target Abort Interrupt Status Flag Note1: This bit is cleared by writing 1 to it. Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. VDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset VDMA controller, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TD_IS : Transfer Done Interrupt Status Flag\nThis bit indicates that VDMA has finished all transfer. \n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SASTOBL : VDMA Source Address Stride Offset Byte Length\nThe 16-bit register defines the source address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write

STBC : VDMA Stride Transfer Byte Count\nThe 16-bit register defines the stride transfer byte count of each row.
bits : 16 - 31 (16 bit)
access : read-write

DASTOBL : VDMA Destination Address Stride Offset Byte Length\nThe 16-bit register defines the destination address stride transfer offset count of each row.
bits : 0 - 15 (16 bit)
access : read-write

VDMA_SAR : VDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of VDMA.
bits : 0 - 31 (32 bit)
access : read-write

VDMA_DAR : VDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of VDMA.
bits : 0 - 31 (32 bit)
access : read-write

VDMA_BUF0 : VDMA Internal Buffer FIFO 0 (Read Only)\nVDMA channel has its own 2 words internal buffer.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_BUF1 : VDMA Internal Buffer FIFO 1 (Read Only)\nVDMA channel has its own 2 words internal buffer.
bits : 0 - 31 (32 bit)
access : read-only

VDMA_BCR : VDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count number of VDMA.\n
bits : 0 - 15 (16 bit)
access : read-write