Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
PDMA Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMACEN : PDMA Channel Enable Control
Setting this bit to 1 enables PDMA operation. If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
bits : 0 - 0 (1 bit)
access : read-write
SW_RST : Software Engine Reset\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal state machine and pointers. The contents of control register will not be cleared. This bit will be automatically cleared after few clock cycles
End of enumeration elements list.
MODE_SEL : PDMA Mode Selection\n
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
Memory to Memory mode (Memory-to-Memory)
#01 : 1
Peripheral to Memory mode (Peripheral-to-Memory)
#10 : 2
Memory to Peripheral mode (Memory-to-Peripheral)
#11 : 3
Reserved
End of enumeration elements list.
SAD_SEL : Transfer Source Address Direction Selection\n
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer Source address is incremented successively
#01 : 1
Reserved
#10 : 2
Transfer Source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations)
#11 : 3
Transfer Source address is wrap around (When the PDMA_CBCR is equal to 0, the PDMA_CSAR and PDMA_CBCR register will be updated by PDMA_SAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address)
End of enumeration elements list.
DAD_SEL : Transfer Destination Address Direction Selection\n
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Transfer Destination address is incremented successively
#01 : 1
Reserved
#10 : 2
Transfer Destination address is fixed (This feature can be used when data where transferred from multiple sources to a single destination)
#11 : 3
Transfer Destination address is wrapped around (When the PDMA_CBCR is equal to 0, the PDMA_CDAR and PDMA_CBCR register will be updated by PDMA_DAR and PDMA_BCR automatically. PDMA will start another transfer without user trigger until PDMA_EN disabled. When the PDMA_EN is disabled, the PDMA will complete the active transfer but the remained data which in the PDMA_BUF will not transfer to destination address)
End of enumeration elements list.
TO_EN : Time-Out Enable Control\nThis bit will enable PDMA internal Counter. While this counter counts to zero, the TO_IS will be set.\n
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA internal counter Disabled
#1 : 1
PDMA internal counter Enabled
End of enumeration elements list.
APB_TWS : Peripheral Transfer Width Selection\nNote: This field is meaningful only when MODE_SEL is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
One word (32-bit) is transferred for every PDMA operation
#01 : 1
One byte (8-bit) is transferred for every PDMA operation
#10 : 2
One half-word (16-bit) is transferred for every PDMA operation
#11 : 3
Reserved
End of enumeration elements list.
TRIG_EN : Trigger Enable Control\nNote: When PDMA transfer completed, this bit will be cleared automatically.\nIf the bus error occurs, all PDMA transfer will be stopped. User must reset all PDMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
PDMA data read or write transfer Enabled
End of enumeration elements list.
PDMA Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_CSAR : PDMA Current Source Address Bits (Read Only)\nThis field indicates the source address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Current Destination Address Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_CDAR : PDMA Current Destination Address Bits (Read Only)\nThis field indicates the destination address where the PDMA transfer just occurred.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_CBCR : PDMA Current Byte Count Bits (Read Only)\nThis field indicates the current remained byte count of PDMA.\nNote: This field will be changed when PDMA finishes data transfer (data transfer to destination address).
bits : 0 - 23 (24 bit)
access : read-only
PDMA Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABORT_IE : PDMA Read/Write Target Abort Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Target abort interrupt generation Disabled during PDMA transfer
#1 : 1
Target abort interrupt generation Enabled during PDMA transfer
End of enumeration elements list.
TD_IE : PDMA Transfer Done Interrupt Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generator Disabled when PDMA transfer is done
#1 : 1
Interrupt generator Enabled when PDMA transfer is done
End of enumeration elements list.
WRA_BCR_IE : Wrap Around Byte Count Interrupt Enable Control\n
bits : 2 - 5 (4 bit)
access : read-write
Enumeration:
#0001 : 1
Interrupt enable of PDMA_CBCR equals 0
#0100 : 4
Interrupt enable of PDMA_CBCR equals 1/2 PDMA_BCR
End of enumeration elements list.
TO_IE : Time-Out Interrupt Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out interrupt Disabled
#1 : 1
Time-out interrupt Enabled
End of enumeration elements list.
PDMA Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABORT_IS : PDMA Read/Write Target Abort Interrupt Status Flag
Note1: This bit is cleared by writing 1 to it.
Note2: This bit indicates bus master received ERROR response or not, if bus master received occur it means that target abort is happened. PDMA controller will stop transfer and respond this event to user then go to IDLE state. When target abort occurred, user must reset PDMA controller, and then transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
TD_IS : Transfer Done Interrupt Status Flag
This bit indicates that PDMA has finished all transfer.
Note: This bit is cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not finished yet
#1 : 1
Done
End of enumeration elements list.
WRA_BCR_IS : Wrap Around Transfer Byte Count Interrupt Status Flag\n
bits : 2 - 5 (4 bit)
access : read-write
TO_IS : Time-Out Interrupt Status Flag
This flag indicated that PDMA has waited peripheral request for a period defined by PDMA_TCR.
Note: This bit is cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No time-out flag
#1 : 1
Time-out flag
End of enumeration elements list.
PDMA Timer Counter Setting Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_TCR : PDMA Timer Count Setting Bits\nEach PDMA channel contains an internal counter. This internal counter will reload and start counting when completing each peripheral request service. The internal counter loads the value of PDAM_TCR and starts counting down when setting TO_EN (PDMA_CSRx[12]). PDMA will request interrupt when this internal counter reaches 0 and TO_IE (PDMA_IERx[6]) is 1.
bits : 0 - 15 (16 bit)
access : read-write
PDMA Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_SAR : PDMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of PDMA.\nNote: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write
PDMA Destination Address Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_DAR : PDMA Transfer Destination Address Bits\nThis field indicates a 32-bit destination address of PDMA.\nNote : The destination address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write
PDMA Internal Buffer FIFO
address_offset : 0x80 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDMA_BUF : PDMA Internal Buffer FIFO (Read Only)\nEach channel has its own 1 word internal buffer.
bits : 0 - 31 (32 bit)
access : read-only
PDMA Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_BCR : PDMA Transfer Byte Count Bits\nThis field indicates a 16-bit transfer byte count of PDMA.\n
bits : 0 - 15 (16 bit)
access : read-write
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