TMR0_CTL (CTL)

TMR0_ISR (ISR)

TMR0_DR (DR)

TMR0_TCAP (TCAP)

GPA_SHADOW

GPB_SHADOW

GPC_SHADOW

GPD_SHADOW

GPE_SHADOW

GPF_SHADOW

TMR0_PRECNT (PRECNT)

TMR0_CMPR (CMPR)

TMR0_IER (IER)

TMR_EN : Timer Counter Enable Bit\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SW_RST : Software Reset Set this bit will reset the timer counter, pre-scale counter and also force TMR_EN (TMRx_CTL[0]) to 0. Note: This bit will auto clear and takes at least 3 TMRx_CLK clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_EN : Wake-Up Enable When WAKE_EN is set and the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set, the timer controller will generate a wake-up trigger event to CPU.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DBGACK_EN : ICE Debug Mode Acknowledge Ineffective Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODE_SEL : Timer Operating Mode Select\n
bits : 4 - 5 (2 bit)
access : read-write

TMR_ACT : Timer Active Status Bit (Read Only)\nThis bit indicates the timer counter status of timer.\n
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADC_TEEN : TMR_IS Or TCAP_IS Trigger ADC Enable\nThis bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger ADC.\nWhen ADC_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to ADC controller.\nWhen ADC_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to ADC controller.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMA_TEEN : TMR_IS Or TCAP_IS Trigger PDMA Enable This bit controls if TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) could trigger PDMA. When PDMA_TEEN is set, TMR_IS (TMRx_ISR[0]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is low, the timer controller will generate an internal trigger event to PDMA controller. When PDMA_TEEN is set, TCAP_IS (TMRx_ISR[1]) is set and the CAP_TRG_EN (TMRx_CTL[11]) is high, the timer controller will generate an internal trigger event to PDMA controller.
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAP_TRG_EN : TCAP_IS Trigger Mode Enable\nThis bit controls if the TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is used to trigger PDMA and ADC while TMR_IS (TMRx_ISR[0]) or TCAP_IS (TMRx_ISR[1]) is set.\nIf this bit is low and TMR_IS (TMRx_ISR[0]) is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN, or ADC_TEEN) is also set.\nIf this bit is set high and TCAP_IS is set, timer will generate an internal trigger event to PDMA or ADC while related trigger enable bit (PDMA_TEEN (TMRx_CTL[10]), or ADC_TEEN(TMRx_CTL[8])) is also set.\n
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EVENT_EN : Event Counting Mode Enable\nWhen EVENT_EN is set, the increase of 24-bit up-counting timer is controlled by external event pin.\nWhile the transition of external event pin matches the definition of EVENT_EDGE (TMRx_CTL[13]), the 24-bit up-counting timer increases by 1. Or, the 24-bit up-counting timer will keep its value unchanged.\n
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EVENT_EDGE : Event Counting Mode Edge Selection\nThis bit indicates which edge of external event pin enabling the timer to increase 1.\n
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EVNT_DEB_EN : External Event De-Bounce Enable\nWhen EVNT_DEB_EN is set, the external event pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the external event pin will be sampled 4 times by TMRx_CLK.\nNote: When EVENT_EN (TMRx_CTL[12]) is enabled, enable this bit is recommended. And, while EVENT_EN (TMRx_CTL[12]) is disabled, disable this bit is recommended to save power consumption.
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP_EN : TCapture Pin Functional Enable This bit controls if the transition on TCapture pin could be used as timer counter reset function or timer capture function. Note: For TMRx_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to low and the TCapture pin transition is ignored. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the TCAP_EN will be forced to high.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP_MODE : TCapture Pin Function Mode Selection\nThis bit indicates if the transition on TCapture pin is used as timer counter reset function or timer capture function.\nNote: For TMRx+1_CTL, if INTR_TRG_EN is set, the TCAP_MODE will be forced to low.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP_EDGE : TCapture Pin Edge Detect Selection\n
bits : 18 - 19 (2 bit)
access : read-write

CAP_CNT_MOD : Timer Capture Counting Mode Selection This bit indicates the behavior of 24-bit up-counting timer while TCAP_EN (TMRx_CTL[16]) is set to high. If this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by MODE_SEL (TMRx_CTL[5:4]) field. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and the transition of Tcapture pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP. If this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at zero. When TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TMRx_TCAP. Note: For TMRx+1_CTL, if INTR_TRG_EN (TMRx_CTL[24]) is set, the CAP_CNT_MOD will be forced to high, the capture with trigger-counting timer mode.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP_DEB_EN : TCapture Pin De-Bounce Enable\nWhen CAP_DEB_EN is set, the TCapture pin de-bounce circuit will be enabled to eliminate the bouncing of the signal.\nIn de-bounce circuit the TCapture pin signal will be sampled 4 times by TMRx_CLK.\nNote: When TCAP_EN (TMRx_CTL[16]) is enabled, enable this bit is recommended. And, while TCAP_EN (TMRx_CTL[16]) is disabled, disable this bit is recommended to save power consumption.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INTR_TRG_EN : Inter-Timer Trigger Mode Enable\nThis bit controls if the inter-timer trigger mode is enabled.\nIf inter-timer trigger mode is enabled, the TMRx will be in counter mode and counting with external Clock Source or event. And, TMRx +1 will be in trigger-counting mode of capture function.\nNote: For TMRx+1_CTL, this bit is ignored and the read back value is always 1'b0.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMR_IS : Timer Interrupt Status\nThis bit indicates the interrupt status of Timer.\nThis bit is set by hardware when the up counting value of internal 24-bit counter matches the timer compared value (TMR_CMPR). Write 1 to clear this bit to zero.\nIf this bit is active and TMR_IE (TMRx_IER[0]) is enabled, Timer will trigger an interrupt to CPU.
bits : 0 - 0 (1 bit)
access : read-write

TCAP_IS : Timer Capture Function Interrupt Status\nThis bit indicates the external pin function interrupt status of Timer.\nThis bit is set by hardware when TCAP_EN (TMRx_CTL[16]) is set high, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting. Write 1 to clear this bit to zero.\nIf this bit is active and TCAP_IE (TMRx_IER[1]) is enabled, Timer will trigger an interrupt to CPU.
bits : 1 - 1 (1 bit)
access : read-write

TMR_Wake_STS : Timer Wake-Up Status\nIf timer causes CPU wakes up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit.\n0: Timer does not cause system wake-up.\n1: Wakes system up from power-down mode by Timer timeout.
bits : 4 - 4 (1 bit)
access : read-write

NCAP_DET_STS : New Capture Detected Status\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status.\nIf the above condition occurred, the Timer will keep register TMRx_CAP unchanged and drop the new capture value.\nThis bit is also cleared to 0 while TCAP_IS (TMRx_ISR[1]) is cleared.\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TDR : Timer Data Register\nUser can read this register for internal 24-bit timer up-counter value.
bits : 0 - 23 (24 bit)
access : read-write

CAP : Timer Capture Data Register\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 0, and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nWhen TCAP_EN (TMRx_CTL[16]) is set, TCAP_MODE (TMRx_CTL[17]) is 0, TCAP_CNT_MOD (TMRx_CTL[20]) is 1, and the transition of external pin matches the 2nd transition of TCAP_EDGE (TMRx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TMRx_TCAP.\nUser can read this register to get the counter value.\nWhen a new incoming capture event detected before CPU clearing the TCAP_IS (TMRx_ISR[1]) status, Timer will keep this filed value unchanged and drop the new capture value.
bits : 0 - 23 (24 bit)
access : read-only

PIN0 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 0 - 0 (1 bit)
access : read-only

PIN1 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 1 - 1 (1 bit)
access : read-only

PIN2 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 2 - 2 (1 bit)
access : read-only

PIN3 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 3 - 3 (1 bit)
access : read-only

PIN4 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 4 - 4 (1 bit)
access : read-only

PIN5 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 5 - 5 (1 bit)
access : read-only

PIN6 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 6 - 6 (1 bit)
access : read-only

PIN7 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 7 - 7 (1 bit)
access : read-only

PIN8 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 8 - 8 (1 bit)
access : read-only

PIN9 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 9 - 9 (1 bit)
access : read-only

PIN10 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 10 - 10 (1 bit)
access : read-only

PIN11 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 11 - 11 (1 bit)
access : read-only

PIN12 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 12 - 12 (1 bit)
access : read-only

PIN13 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 13 - 13 (1 bit)
access : read-only

PIN14 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 14 - 14 (1 bit)
access : read-only

PIN15 : GPIO Port [A/B/C/D/E/F] Pin Values\nThe value read from each of these bit reflects the actual status of the respective GPIO pin.\nThese registers are shadow registers of GPIOx_PIN register.\nNote: For GPF_SHADOW, bits [15:9] are reserved.
bits : 15 - 15 (1 bit)
access : read-only

PRESCALE_CNT : Pre-Scale Counter\n
bits : 0 - 7 (8 bit)
access : read-write

TMR_CMP : Timer Compared Value\nTMR_CMP is a 24-bit compared register. When the internal 24-bit up-counter counts and its value is equal to TMR_CMP value, a Timer Interrupt is requested if the timer interrupt is enabled with TMR_EN (TMRx_CTL[0]) is enabled. The TMR_CMP value defines the timer counting cycle time.\nNote1: Never write 0 or 1 in TMR_CMP, or the core will run into unknown state.\nNote2: No matter TMR_EN (TMRx_CTL[0]) is 0 or 1, whenever software write a new value into this register, TIMER will restart counting using this new value and abort previous count.
bits : 0 - 23 (24 bit)
access : read-write

TMR_IE : Timer Interrupt Enable\nNOTE: If timer interrupt is enabled, the timer asserts its interrupt signal when the associated counter is equal to TMR_CMPR.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCAP_IE : Timer Capture Function Interrupt Enable\nNOTE: If timer external pin function interrupt is enabled, the timer asserts its interrupt signal when the TCAP_EN (TMRx_CTL[16]) is set and the transition of external pin matches the TCAP_EDGE (TMRx_CTL[19:18])setting.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.