PWM0_PRES (PRES)

PWM1_PRES

PWM0_INTSTS (INTSTS)

PWM1_INTSTS

PWM0_OE (OE)

PWM1_OE

PWM0_DUTY0 (DUTY0)

PWM1_DUTY0

PWM0_DATA0 (DATA0)

PWM1_DATA0

PWM0_DUTY1 (DUTY1)

PWM1_DUTY1

PWM0_DATA1 (DATA1)

PWM1_DATA1

PWM0_DUTY2 (DUTY2)

PWM1_DUTY2

PWM0_DATA2 (DATA2)

PWM1_DATA2

PWM0_CLKSEL (CLKSEL)

PWM1_CLKSEL

PWM0_DUTY3 (DUTY3)

PWM1_DUTY3

PWM0_DATA3 (DATA3)

PWM1_DATA3

PWM0_CAPCTL (CAPCTL)

PWM1_CAPCTL

PWM0_CAPINTEN (CAPINTEN)

PWM1_CAPINTEN

PWM0_CAPINTSTS (CAPINTSTS)

PWM1_CAPINTSTS

PWM0_CRL0 (CRL0)

PWM1_CRL0

PWM0_CFL0 (CFL0)

PWM1_CFL0

PWM0_CRL1 (CRL1)

PWM1_CRL1

PWM0_CFL1 (CFL1)

PWM1_CFL1

PWM0_CRL2 (CRL2)

PWM1_CRL2

PWM0_CFL2 (CFL2)

PWM1_CFL2

PWM0_CRL3 (CRL3)

PWM1_CRL3

PWM0_CFL3 (CFL3)

PWM1_CFL3

PWM0_CTL (CTL)

PWM1_CTL

PWM0_PDMACH0 (PDMACH0)

PWM1_PDMACH0

PWM0_PDMACH2 (PDMACH2)

PWM1_PDMACH2

PWM0_INTEN (INTEN)

PWM1_INTEN

CP01 : Clock Prescaler 0 For PWM Timer 0 1 Clock input is divided by (CP01 + 1) before it is fed to the counter 0 1
bits : 0 - 7 (8 bit)
access : read-write

CP23 : Clock Prescaler 2 For PWM Timer 2 3 Clock input is divided by (CP23 + 1) before it is fed to the counter 2 3
bits : 8 - 15 (8 bit)
access : read-write

DZ01 : Dead Zone Interval Register For CH0 And CH1 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 0.
bits : 16 - 23 (8 bit)
access : read-write

DZ23 : Dead Zone Interval Register For CH2 And CH3 Pair\nThese 8 bits determine dead zone length.\nThe unit time of dead zone length is received from clock selector 2.
bits : 24 - 31 (8 bit)
access : read-write

TMINT0 : PWM Timer 0 Interrupt Flag\nFlag is set by hardware when PWM0 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 0 - 0 (1 bit)
access : read-write

TMINT1 : PWM Timer 1 Interrupt Flag\nFlag is set by hardware when PWM1 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 1 - 1 (1 bit)
access : read-write

TMINT2 : PWM Timer 2 Interrupt Flag\nFlag is set by hardware when PWM2 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 2 - 2 (1 bit)
access : read-write

TMINT3 : PWM Timer 3 Interrupt Flag\nFlag is set by hardware when PWM3 down counter reaches zero, software can clear this bit by writing a one to it.
bits : 3 - 3 (1 bit)
access : read-write

Duty0Syncflag : Duty0 Synchronize Flag\nNote: software should check this flag when writing duty0, if this flag is set, and user ignore this flag and change duty0, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Duty1Syncflag : Duty1 Synchronize Flag\nNote: software should check this flag when writing duty1, if this flag is set, and user ignore this flag and change duty1, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Duty2Syncflag : Duty2 Synchronize Flag\nNote: software should check this flag when writing duty2, if this flag is set, and user ignore this flag and change duty2, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

Duty3Syncflag : Duty3 Synchronize Flag\nNote: software should check this flag when writing duty3, if this flag is set, and user ignore this flag and change duty3, the corresponding CNR and CMR may be wrong for one duty cycle
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PresSyncFlag : Prescale Synchronize Flag Note: software should check this flag when writing Prescale, if this flag is set, and user ignore this flag and change Prescale, the Prescale may be wrong for one prescale cycle
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0_OE : PWM CH0 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH1_OE : PWM CH1 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2_OE : PWM CH2 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH3_OE : PWM CH3 Output Enable Register\nNote: The corresponding GPIO pin also must be switched to PWM function (refer to GPx_MFP)
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CN : PWM Counter/Timer Loaded Value\nCN determines the PWM period.\nNote: \nAny write to CN will take effect in next PWM cycle.
bits : 0 - 15 (16 bit)
access : read-write

CM : PWM Comparator Register\nCM determines the PWM duty.\nNote:\n Any write to CM will take effect in next PWM cycle.
bits : 16 - 31 (16 bit)
access : read-write

DATA : PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 16-bit down count counter of corresponding channel y.
bits : 0 - 15 (16 bit)
access : read-only

DATA_H : PWM Data Register\nUser can monitor PWMx_DATAy to know the current value in 32-bit down count counter of corresponding channel y.\nNotes:This will be valid only for the corresponding cascade enable bit is set
bits : 16 - 30 (15 bit)
access : read-only

sync : Indicate That CNR Value Is Sync To PWM Counter\nNote: when the corresponding cascade enable .bit is set is bit will not appear in the corresponding channel
bits : 31 - 31 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CLKSEL0 : Timer 0 Clock Source Selection\nSelect clock input for timer 0.\n(Table is the same as CLKSEL3)
bits : 0 - 2 (3 bit)
access : read-write

CLKSEL1 : Timer 1 Clock Source Selection\nSelect clock input for timer 1.\n(Table is the same as CLKSEL3)
bits : 4 - 6 (3 bit)
access : read-write

CLKSEL2 : Timer 2Clock Source Selection\nSelect clock input for timer 2.\n(Table is the same as CLKSEL3)
bits : 8 - 10 (3 bit)
access : read-write

CLKSEL3 : Timer 3 Clock Source Selection\nSelect clock input for timer 3.\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV0 : Channel 0 Inverter ON/OFF\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0EN : Capture Channel 0 Transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWMx_CRL0 (Rising latch) and PWMx_CFL0 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL0 and PWMx_CFL0, and disable Channel 0 Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH0PADEN : Capture Input Enable Register\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0PDMAEN : Channel 0 PDMA Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMACAPMOD0 : Select CRL0 Or CFL0 For PDMA Transfer\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADREN0 : Reload CNR0 When CH0 Capture Rising Event Comes \n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN0 : Reload CNR0 When CH0 Capture Falling Event Comes\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV1 : Channel 1 Inverter ON/OFF\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1EN : Capture Channel 1 Transition Enable/Disable\nWhen Enabled, Capture latched the PMW-counter and saved to PWMx_CRL1 (Rising latch) and PWMx_CFL1 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL1 and PWMx_CFL1, and disable Channel 1 Interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH1PADEN : Capture Input Enable Register\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH0RFORDER : None
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH01CASK : Cascade channel 0 and channel 1 PWM timer for capturing usage
bits : 13 - 13 (1 bit)
access : read-write

CAPRELOADREN1 : Reload CNR1 When CH1 Capture Rising Event Comes\n
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN1 : Reload CNR1 When CH1 Capture Falling Event Coming \n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV2 : Channel 2 Inverter ON/OFF\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH2EN : Capture Channel 2 Transition Enable/Disable\nWhen Enabled, Capture latched the PWM-timer value and saved to PWMx_CRL2 (Rising latch) and PWMx_CFL2 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL2 and PWMx_CFL2, and disable Channel 2 Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH2PADEN : Capture Input Enable Register\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2PDMAEN : Channel 2 PDMA Enable\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PDMACAPMOD2 : Select CRL2 Or CFL2 For PDMA Transfer\n
bits : 20 - 21 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADREN2 : Reload CNR2 When CH2 Capture Rising Event Coming \n
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN2 : Reload CNR2 When CH2 Capture Failing Event Coming \n
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV3 : Channel 3 Inverter ON/OFF\n
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH3EN : Capture Channel 3 Transition Enable/Disable\nWhen Enabled, Capture latched the PMW-timer and saved to PWMx_CRL3 (Rising latch) and PWMx_CFL3 (Falling latch).\nWhen Disabled, Capture does not update PWMx_CRL3 and PWMx_CFL3, and disable Channel 3 Interrupt.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPCH3PADEN : Capture Input Enable Register\n
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH2RFORDER : None
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH23CASK : Cascade channel 2 and channel 3 PWM counter for capturing usage
bits : 29 - 29 (1 bit)
access : read-write

CAPRELOADREN3 : Reload CNR3 When CH3 Rising Capture Event Comes\n
bits : 30 - 30 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPRELOADFEN3 : Reload CNR3 When CH3 Falling Capture Event Comes \n
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE0 : When Enabled, if Capture detects Channel 0 has rising transition, Capture issues an Interrupt.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE0 : Channel 0 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 0 has falling transition, Capture issues an Interrupt.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE1 : Channel 1 Rising Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has rising transition, Capture issues an Interrupt.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE1 : Channel 1 Falling Latch Interrupt Enable \nWhen Enabled, if Capture detects Channel 1 has falling transition, Capture issues an Interrupt.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE2 : Channel 2 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has rising transition, Capture issues an Interrupt.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE2 : Channel 2 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 2 has falling transition, Capture issues an Interrupt.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRL_IE3 : Channel 3 Rising Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has rising transition, Capture issues an Interrupt.
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFL_IE3 : Channel 3 Falling Latch Interrupt Enable ON/OFF\nWhen Enabled, if Capture detects Channel 3 has falling transition, Capture issues an Interrupt.
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CAPIF0 : Capture0 Interrupt Indication Flag If channel 0 rising latch interrupt (CRL_IE0, PWMx_CAPINTEN[0]) is enabled, a rising transition occurs at input channel 0 will result in CAPIF0 to high Similarly, a falling transition will cause CAPIF0 to be set high if channel 0 falling latch interrupt (CFL_IE0, PWMx_CAPINTEN[1]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 0 - 0 (1 bit)
access : read-write

CRLI0 : PWM_CRL0 Latched Indicator Bit\nWhen input channel 0 has a rising transition, PWMx_CRL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

CFLI0 : PWM_CFL0 Latched Indicator Bit\nWhen input channel 0 has a falling transition, PWMx_CFL0 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

CAPOVR0 : Capture Rising Flag Over Run For Channel 0\nThis flag indicate CRL0 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clears CRLI0 (PWMx_CAPINTSTS[1]).
bits : 3 - 3 (1 bit)
access : read-write

CAPOVF0 : Capture Falling Flag Over Run For Channel 0\nThis flag indicate CFL0 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI0 (PWMx_CAPINTSTS[2])
bits : 4 - 4 (1 bit)
access : read-write

CAPIF1 : Capture1 Interrupt Indication Flag If channel 1 rising latch interrupt (CRL_IE1, PWMx_CAPINTEN[8]) is enabled, a rising transition occurs at input channel 1 will result in CAPIF1 to high Similarly, a falling transition will cause CAPIF1 to be set high if channel 1 falling latch interrupt (CFL_IE1, PWMx_CAPINTEN[9]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 8 - 8 (1 bit)
access : read-write

CRLI1 : PWM_CRL1 Latched Indicator Bit\nWhen input channel 1 has a rising transition, PWMx_CRL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 9 - 9 (1 bit)
access : read-write

CFLI1 : PWM_CFL1 Latched Indicator Bit\nWhen input channel 1 has a falling transition, PWMx_CFL1 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing a 1 to it.
bits : 10 - 10 (1 bit)
access : read-write

CAPOVR1 : Capture Rising Flag Over Run For Channel 1\nThis flag indicate CRL1 update faster than software reading it when it is set \nThis bit will be cleared automatically when user clear CRLI1 (PWMx_CAPINTSTS[9])
bits : 11 - 11 (1 bit)
access : read-write

CAPOVF1 : Capture Falling Flag Over Run For Channel 1\nThis flag indicate CFL1 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI1 (PWMx_CAPINTSTS[10])
bits : 12 - 12 (1 bit)
access : read-write

CAPIF2 : Capture2 Interrupt Indication Flag If channel 2 rising latch interrupt (CRL_IE2, PWMx_CAPINTEN[16]) is enabled, a rising transition occurs at input channel 2 will result in CAPIF2 to high Similarly, a falling transition will cause CAPIF2 to be set high if channel 2 falling latch interrupt (CFL_IE2, PWMx_CAPINTEN[17]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 16 - 16 (1 bit)
access : read-write

CRLI2 : PWM_CRL2 Latched Indicator Bit\nWhen input channel 2 has a rising transition, PWMx_CRL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 17 - 17 (1 bit)
access : read-write

CFLI2 : PWM_CFL2 Latched Indicator Bit\nWhen input channel 2 has a falling transition, PWMx_CFL2 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-write

CAPOVR2 : Capture Rising Flag Over Run For Channel 2\nThis flag indicate CRL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI2 (PWMx_CAPINTSTS[17])
bits : 19 - 19 (1 bit)
access : read-write

CAPOVF2 : Capture Falling Flag Over Run For Channel 2 \nThis flag indicate CFL2 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI2 (PWMx_CAPINTSTS[18])
bits : 20 - 20 (1 bit)
access : read-write

CAPIF3 : Capture3 Interrupt Indication Flag If channel 3 rising latch interrupt (CRL_IE3, PWMx_CAPINTEN[24]) is enabled, a rising transition occurs at input channel 3 will result in CAPIF3 to high Similarly, a falling transition will cause CAPIF3 to be set high if channel 3 falling latch interrupt (CFL_IE3, PWMx_CAPINTEN[25]) is enabled. This flag is cleared by software with a write 1 on it.
bits : 24 - 24 (1 bit)
access : read-write

CRLI3 : PWM_CRL3 Latched Indicator Bit\nWhen input channel 3 has a rising transition, PWMx_CRL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 25 - 25 (1 bit)
access : read-write

CFLI3 : PWM_CFL3 Latched Indicator Bit\nWhen input channel 3 has a falling transition, PWMx_CFL3 was latched with the value of PWM down-counter and this bit is set by hardware, software can clear this bit by writing 1 to it.
bits : 26 - 26 (1 bit)
access : read-write

CAPOVR3 : Capture Rising Flag Over Run For Channel 3\nThis flag indicate CRL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CRLI3 (PWMx_CAPINTSTS[25])
bits : 27 - 27 (1 bit)
access : read-write

CAPOVF3 : Capture Falling Flag Over Run For Channel 3 \nThis flag indicate CFL3 update faster than software reading it when it is set\nThis bit will be cleared automatically when user clear CFLI3 (PWMx_CAPINTSTS[26])
bits : 28 - 28 (1 bit)
access : read-write

CRL : Capture Rising Latch Register\nLatch the PWM counter when Channel 0/1/2/3 has rising transition.
bits : 0 - 15 (16 bit)
access : read-only

CRL_H : Upper Half Word Of 32-Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CRL0 and CRL2 are also extend to 32 bit,
bits : 16 - 31 (16 bit)
access : read-only

CFL : Capture Falling Latch Register\nLatch the PWM counter when Channel 01/2/3 has Falling transition.
bits : 0 - 15 (16 bit)
access : read-only

CFL_H : Upper Half Word Of 32 Bit Capture Data When Cascade Is Enable \nWhen cascade is enabled for capture channel 0, 2,the original 16 bit counter extend to 32 bit, and capture result CFL0 and CFL2 are also extend to 32 bit,
bits : 16 - 31 (16 bit)
access : read-only