\n

WDT

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected

Registers

WDT_CTL (CTL)

WDT_IER (IER)

WDT_ISR (ISR)


WDT_CTL (CTL)

Watchdog Timer Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDT_CTL WDT_CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WTR WTRE WTWKE WTE WTIS

WTR : Clear Watchdog Timer (Write Protect)\nPlease refer to open lock sequence to program it.\nSet this bit will clear the Watchdog timer. \nNote: This bit will auto clear after few clock cycle
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No effect

#1 : 1

Reset the contents of the Watchdog timer

End of enumeration elements list.

WTRE : Watchdog Timer Reset Function Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\nSetting this bit will enable the Watchdog timer reset function.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer reset function Disabled

#1 : 1

Watchdog timer reset function Enabled

End of enumeration elements list.

WTWKE : Watchdog Timer Wake-Up Function Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer Wake-up CPU function Disabled

#1 : 1

Wake-up function Enabled so that Watchdog timer time-out can wake up CPU from power-down mode

End of enumeration elements list.

WTE : Watchdog Timer Enable Control (Write Protect)\nPlease refer to open lock sequence to program it.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer Disabled (this action will reset the internal counter)

#1 : 1

Watchdog timer Enabled

End of enumeration elements list.

WTIS : Watchdog Timer Interval Selection (Write Protect)\nPlease refer to open lock sequence to program it.\nThe three bits select the time-out interval for the Watchdog timer. This count is free running counter.\nPlease refer to Table 5.191 Watchdog Time-out Interval Selection
bits : 4 - 6 (3 bit)
access : read-write


WDT_IER (IER)

Watchdog Timer Interrupt Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDT_IER WDT_IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_IE

WDT_IE : Watchdog Timer Interrupt Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Watchdog timer interrupt Disabled

#1 : 1

Watchdog timer interrupt Enabled

End of enumeration elements list.


WDT_ISR (ISR)

Watchdog Timer Interrupt Status Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDT_ISR WDT_ISR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_IS WDT_RST_IS WDT_WAKE_IS

WDT_IS : Watchdog Timer Interrupt Status (Read Only) If the Watchdog timer interrupt is enabled, then the hardware will set this bit to indicate that the Watchdog timer interrupt has occurred. If the Watchdog timer interrupt is not enabled, then this bit indicates that a time-out period has elapsed. Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

Watchdog timer interrupt does not occur

#1 : 1

Watchdog timer interrupt occurs

End of enumeration elements list.

WDT_RST_IS : Watchdog Timer Reset Status (Read Only) When the Watchdog timer initiates a reset, the hardware will set this bit. This flag can be read by software to determine the source of reset. Software is responsible to clear it manually by writing 1 to it. If WTRE is disabled, then the Watchdog timer has no effect on this bit. Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#0 : 0

Watchdog timer reset does not occur

#1 : 1

Watchdog timer reset occurs

End of enumeration elements list.

WDT_WAKE_IS : Watchdog Timer Wake-Up Status (Read Only) If Watchdog timer causes system to wake up from power-down mode, this bit will be set to high. It must be cleared by software with a write 1 to this bit. Note1: When system in power-down mode and watchdog time-out, hardware will set WDT_WAKE_IS and WDT_IS. Note2: After one engine clock., this bit can be cleared by writing 1 to it
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

#0 : 0

Watchdog timer does not cause system wake-up

#1 : 1

Wake system up from power-down mode by Watchdog time-out

End of enumeration elements list.



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