\n

RTC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x3C Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RTC_INIR (INIR)

RTC_CLR (CLR)

RTC_TSSR (TSSR)

RTC_DWR (DWR)

RTC_TAR (TAR)

RTC_CAR (CAR)

RTC_LIR (LIR)

RTC_RIER (RIER)

RTC_RIIR (RIIR)

RTC_TTR (TTR)

RTC_SPRCTL (SPRCTL)

RTC_AER (AER)

RTC_SPR0 (SPR0)

RTC_SPR1 (SPR1)

RTC_SPR2 (SPR2)

RTC_SPR3 (SPR3)

RTC_SPR4 (SPR4)

RTC_SPR5 (SPR5)

RTC_SPR6 (SPR6)

RTC_SPR7 (SPR7)

RTC_SPR8 (SPR8)

RTC_SPR9 (SPR9)

RTC_SPR10 (SPR10)

RTC_SPR11 (SPR11)

RTC_SPR12 (SPR12)

RTC_SPR13 (SPR13)

RTC_SPR14 (SPR14)

RTC_SPR15 (SPR15)

RTC_FCR (FCR)

RTC_SPR16 (SPR16)

RTC_SPR17 (SPR17)

RTC_SPR18 (SPR18)

RTC_SPR19 (SPR19)

RTC_TLR (TLR)


RTC_INIR (INIR)

RTC Initiation Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_INIR RTC_INIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INIR

INIR : RTC Initiation (Write Only) When RTC block is powered on, RTC is at reset state. User has to write a number (0x a5eb1357) to INIR to make RTC leaving reset state. Once the INIR is written as 0xa5eb1357, the RTC will be in un-reset state permanently. The INIR is a write-only field and read value will be always 0 . RTC Active Status (Read Only),
bits : 0 - 31 (32 bit)
access : write-only

Enumeration:

0 : 0

RTC is at reset state

1 : 1

RTC is at normal active state

End of enumeration elements list.


RTC_CLR (CLR)

Calendar Loading Register
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CLR RTC_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1DAY _10DAY _1MON _10MON _1YEAR _10YEAR

_1DAY : 1 Day Calendar Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10DAY : 10 Day Calendar Digit (0~3)
bits : 4 - 5 (2 bit)
access : read-write

_1MON : 1 Month Calendar Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MON : 10 Month Calendar Digit (0~1)
bits : 12 - 12 (1 bit)
access : read-write

_1YEAR : 1 Year Calendar Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10YEAR : 10 Year Calendar Digit (0~9)
bits : 20 - 23 (4 bit)
access : read-write


RTC_TSSR (TSSR)

Time Scale Selection Register
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TSSR RTC_TSSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _24hr_12hr

_24hr_12hr : 24-Hour / 12-Hour Mode Selection\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

select 12-hour time scale with AM and PM indication

#1 : 1

select 24-hour time scale

End of enumeration elements list.


RTC_DWR (DWR)

Day of the Week Register
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_DWR RTC_DWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DWR

DWR : Day Of The Week Register \n
bits : 0 - 2 (3 bit)
access : read-write


RTC_TAR (TAR)

Time Alarm Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TAR RTC_TAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1SEC _10SEC _1MIN _10MIN _1HR _10HR

_1SEC : 1 Sec Time Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10SEC : 10 Sec Time Digit of Alarm Setting (0~5)
bits : 4 - 6 (3 bit)
access : read-write

_1MIN : 1 Min Time Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MIN : 10 Min Time Digit of Alarm Setting (0~5)
bits : 12 - 14 (3 bit)
access : read-write

_1HR : 1 Hour Time Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10HR : 10 Hour Time Digit of Alarm Setting (0~2)
bits : 20 - 21 (2 bit)
access : read-write


RTC_CAR (CAR)

Calendar Alarm Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_CAR RTC_CAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1DAY _10DAY _1MON _10MON _1YEAR _10YEAR

_1DAY : 1 Day Calendar Digit of Alarm Setting (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10DAY : 10 Day Calendar Digit of Alarm Setting (0~3)
bits : 4 - 5 (2 bit)
access : read-write

_1MON : 1 Month Calendar Digit of Alarm Setting (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MON : 10 Month Calendar Digit of Alarm Setting (0~1)
bits : 12 - 12 (1 bit)
access : read-write

_1YEAR : 1 Year Calendar Digit of Alarm Setting (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10YEAR : 10 Year Calendar Digit of Alarm Setting (0~9)
bits : 20 - 23 (4 bit)
access : read-write


RTC_LIR (LIR)

RTC Leap Year Indication Register
address_offset : 0x24 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RTC_LIR RTC_LIR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIR

LIR : Leap Year Indication REGISTER (Read Only)\n
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#0 : 0

This year is not a leap year

#1 : 1

This year is leap year

End of enumeration elements list.


RTC_RIER (RIER)

RTC Interrupt Enable Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_RIER RTC_RIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIER TIER SNOOPIER

AIER : Alarm Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Alarm Interrupt is disabled

#1 : 1

RTC Alarm Interrupt is enabled

End of enumeration elements list.

TIER : Time Tick Interrupt And Wake-Up By Tick Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

RTC Time Tick Interrupt is disabled

#1 : 1

RTC Time Tick Interrupt is enabled

End of enumeration elements list.

SNOOPIER : Snooper Pin Event Detection Interrupt Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Snooper Pin Event Detection Interrupt is disabled

#1 : 1

Snooper Pin Event Detection Interrupt is enabled

End of enumeration elements list.


RTC_RIIR (RIIR)

RTC Interrupt Indicator Register
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_RIIR RTC_RIIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AIS TIS SNOOPIS

AIS : RTC Alarm Interrupt Status RTC unit will set AIF to high once the RTC real time counters TLR and CLR reach the alarm setting time registers TAR and CAR. When this bit is set and AIER is also high, RTC will generate an interrupt to CPU. This bit is software clear by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Indicates RCT Alarm Interrupt condition never occurred

#1 : 1

Indicates RTC Alarm Interrupt is requested if RIER.AIER=1

End of enumeration elements list.

TIS : RTC Time Tick Interrupt Status RTC unit will set TIF to high periodically in the period selected by TTR(RTC_TTR[2:0]). When this bit is set and TIER is also high, RTC will generate an interrupt to CPU. This bit is software clear by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Indicates RCT Time Tick Interrupt condition never occurred

#1 : 1

Indicates RTC Time Tick Interrupt is requested

End of enumeration elements list.

SNOOPIS : Snooper Pin Event Detection Interrupt Status When SNOOPEN is high and an event defined by SNOOPEDGE detected in snooper pin, this flag will be set. While this bit is set and SNOOPIER is also high, RTC will generate an interrupt to CPU. Write 1 to clear this bit to 0 .
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Snooper pin event defined by SNOOPEDGE never detected

#1 : 1

Snooper pin event defined by SNOOPEDGE detected

End of enumeration elements list.


RTC_TTR (TTR)

RTC Time Tick Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TTR RTC_TTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TTR TWKE

TTR : Time Tick Register\n
bits : 0 - 2 (3 bit)
access : read-write

TWKE : RTC Timer Wake-Up CPU Function Enable Bit\nIf TWKE is set before CPU enters power-down mode, when a RTC Time Tick, CPU will be wakened up by RTC unit.\nNote: Tick timer setting follows the TTR description.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

Time Tick wake-up CPU function Disabled

#1 : 1

Wake-up function Enabled so that CPU can be waken up from Power-down mode by Time Tick

End of enumeration elements list.


RTC_SPRCTL (SPRCTL)

RTC Spare Functional Control Register
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPRCTL RTC_SPRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNOOPEN SNOOPEDGE SPRRDY

SNOOPEN : Snooper Pin Event Detection Enable This bit enables the snooper pin event detection. When this bit is set high and an event defined by SNOOPEDGE detected, the 20 spare registers will be cleared to 0 by hardware automatically. And, the SNOOPIF will also be set. In addition, RTC will also generate wake-up event to wake system up.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Snooper pin event detection function Disabled

#1 : 1

Snooper pin event detection function Enabled

End of enumeration elements list.

SNOOPEDGE : Snooper Active Edge Selection\nThis bit defines which edge of snooper pin will generate a snooper pin detected event to clear the 20 spare registers.\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Rising edge of snooper pin generates snooper pin detected event

#1 : 1

Falling edge of snooper pin generates snooper pin detected event

End of enumeration elements list.

SPRRDY : SPR Register Ready\nThis bit indicates if the registers SPR0 ~ SPR19 are ready to read.\nAfter CPU writing registers SPR0 ~ SPR19, polling this bit to check if SP0 ~ SPR19 are updated done is necessary.\nThis it is a read only bit and any write to this bit won't take any effect.\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

SPR0 ~ SPR19 updating is in progress

#1 : 1

SPR0 ~ SPR19 are updated done and ready to read

End of enumeration elements list.


RTC_AER (AER)

RTC Access Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_AER RTC_AER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AER ENF

AER : RTC Register Access Enable Password (Write Only)\n
bits : 0 - 15 (16 bit)
access : write-only

Enumeration:

0xa965 : 43365

Enable RTC acces.s

End of enumeration elements list.

ENF : RTC Register Access Enable Flag (Read Only)\n
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#0 : 0

RTC register read/write disable

#1 : 1

RTC register read/write enable

End of enumeration elements list.


RTC_SPR0 (SPR0)

RTC Spare Register 0
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR0 RTC_SPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPARE

SPARE : SPARE\nThis field is used to store back-up information defined by software.\nThis field will be cleared by hardware automatically once a snooper pin event is detected.
bits : 0 - 31 (32 bit)
access : read-write


RTC_SPR1 (SPR1)

RTC Spare Register 1
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR1 RTC_SPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR2 (SPR2)

RTC Spare Register 2
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR2 RTC_SPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR3 (SPR3)

RTC Spare Register 3
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR3 RTC_SPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR4 (SPR4)

RTC Spare Register 4
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR4 RTC_SPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR5 (SPR5)

RTC Spare Register 5
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR5 RTC_SPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR6 (SPR6)

RTC Spare Register 6
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR6 RTC_SPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR7 (SPR7)

RTC Spare Register 7
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR7 RTC_SPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR8 (SPR8)

RTC Spare Register 8
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR8 RTC_SPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR9 (SPR9)

RTC Spare Register 9
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR9 RTC_SPR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR10 (SPR10)

RTC Spare Register 10
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR10 RTC_SPR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR11 (SPR11)

RTC Spare Register 11
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR11 RTC_SPR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR12 (SPR12)

RTC Spare Register 12
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR12 RTC_SPR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR13 (SPR13)

RTC Spare Register 13
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR13 RTC_SPR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR14 (SPR14)

RTC Spare Register 14
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR14 RTC_SPR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR15 (SPR15)

RTC Spare Register 15
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR15 RTC_SPR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_FCR (FCR)

RTC Frequency Compensation Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_FCR RTC_FCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRACTION INTEGER

FRACTION : Fraction Part\nNote: Digit in FCR must be expressed as hexadecimal number.
bits : 0 - 5 (6 bit)
access : read-write

INTEGER : Integer Part\n
bits : 8 - 11 (4 bit)
access : read-write


RTC_SPR16 (SPR16)

RTC Spare Register 16
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR16 RTC_SPR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR17 (SPR17)

RTC Spare Register 17
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR17 RTC_SPR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR18 (SPR18)

RTC Spare Register 18
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR18 RTC_SPR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_SPR19 (SPR19)

RTC Spare Register 19
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_SPR19 RTC_SPR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_TLR (TLR)

Time Loading Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTC_TLR RTC_TLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 _1SEC _10SEC _1MIN _10MIN _1HR _10HR

_1SEC : 1 Sec Time Digit (0~9)
bits : 0 - 3 (4 bit)
access : read-write

_10SEC : 10 Sec Time Digit (0~5)
bits : 4 - 6 (3 bit)
access : read-write

_1MIN : 1 Min Time Digit (0~9)
bits : 8 - 11 (4 bit)
access : read-write

_10MIN : 10 Min Time Digit (0~5)
bits : 12 - 14 (3 bit)
access : read-write

_1HR : 1 Hour Time Digit (0~9)
bits : 16 - 19 (4 bit)
access : read-write

_10HR : 10 Hour Time Digit (0~2)
bits : 20 - 21 (2 bit)
access : read-write



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