UART_RBR

UART_THR

UART_ISR

UART_TRSR

UART_FSR

UART_MCSR

UART_TMCTL

UART_BAUD

UART_IRCR

UART_ALT_CTL

UART_FUN_SEL

UART_CTL

UART_TLCTL

UART_IER

RBR : Receive Buffer Register\nBy reading this register, the UART will return an 8-bit data received from RX pin (LSB first).
bits : 0 - 7 (8 bit)
access : read-only

THR : Transmit Holding Register\nBy writing to this register, the UART will send out an 8-bit data through the TX pin (LSB first).
bits : 0 - 7 (8 bit)
access : write-only

RDA_IS : Receive Data Available Interrupt Flag (Read Only) When the number of bytes in the RX-FIFO equals the RFITL then the RDA_IF will be set. If RDA_IEN (IER [0]) is set then the RDA interrupt will be generated. Note: This bit is read only and it will be cleared when the number of unread bytes of RX-FIFO drops below the threshold level (RFITL).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRE_IS : Transmit Holding Register Empty Interrupt Flag (Read Only) \nThis bit is set when the last data of TX-FIFO is transferred to Transmitter Shift Register. If THRE_IEN (IER [1]) is set that the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into THR (TX-FIFO not empty).
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLS_IS : Receive Line Interrupt Status Flag (Read Only) This bit is set when the RX received data has parity error (PE_F (UART_FSR[4])), framing error (FE_F (UART_FSR[5])), break error (BI_F (UART_FSR[6])) or RS-485 detect address byte (RS-485_ADDET_F (UART_TRSR[0])).If RLS_IE (UART_IER[2]) is set then the RLS interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BI_F (UART_FSR[6]), FE_F (UART_FSR[5]), PE_F (UART_FSR[4]) or RS-485_ADDET_F (UART_TRSR[0]). Note2: This bit is cleared when both that the BI_F, FE_F, PE_F and RS-485_ADDET_F are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEM_IS : MODEM Interrupt Status Flag (Read Only) Note: This bit is read only, but can be cleared by it by writing 1 to DCT_F (UART_MCSR [18]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RTO_IS : RX Time-Out Interrupt Status Flag (Read Only)\nThis bit is set when the RX-FIFO is not empty and no activities occur in the RX-FIFO and the time-out counter equal to TOIC. If Tout_IEN (IER [4]) is set then the tout interrupt will be generated. \nNote: This bit is read only and user can read UART_RBR (RX is in active) to clear it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUF_ERR_IS : Buffer Error Interrupt Status Flag (Read Only) This bit is set when the TX or RX-FIFO overflowed. When BUF_ERR_IS is set, the transfer maybe not correct. If BUF_ER_IEN (IER [5]) is set then the buffer error interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to TX_OVER_F (UART_FSR[8]) or RX_OVER_F (UART_FSR[0]). Note2: This bit is cleared when both that the TX_OVER_F and RX_OVER_F are cleared.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WAKE_IS : Wake-Up Interrupt Status Flag This bit is set in Power-down mode, the receiver received data or CTSn signal. If WAKE_IE (IER [6]) is set then the wake-up interrupt will be generated. Note: This bit can be cleared by it by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_IS : Auto-Baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABAUD_IE (IER [7]) is set then the auto-baud rate interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to ABAUD_TOUT_F (UART_TRSR[2]) or ABAUD_F (UART_TRSR[1]). Note2: This bit is cleared when both that the ABAUD_TOUT_F and ABAUD_F are cleared.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LIN_IS : LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LIN_IE (IER [8]) is set then the LIN interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BIT_ERR_F (UART_TRSR[5]), LIN_TX_F (UART_TRSR[3]) or LIN_RX_F (UART_TRSR[4]). Note2: This bit is cleared when both that the BIT_ERR_F, BIT_TX_F and LIN_RX_F are cleared.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RS_485_ADDET_F : RS-485 Address Byte Detection Status Flag Note1: This field is used for RS-485 mode. Note2: This bit can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_F : Auto-Baud Rate Interrupt This bit is set to logic 1 when auto-baud rate detect function finished. Note: This bit can be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_TOUT_F : Auto-Baud Rate Time-Out Interrupt This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note: This bit can be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_F : LIN TX Interrupt Flag This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL[5:4]) register. Note: This bit can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_RX_F : LIN RX Interrupt Flag This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LIN_HEAD_SEL (UART_ALT_CTL [5:4]) register. Note: This bit can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIT_ERR_F : Bit Error Detect Status Flag\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BIT_ERR_F will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (INT_LIN).\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_RX_SYNC_ERR_F : LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting UART_ALT_CTL [LIN_HEAD_SEL] register. Note: This bit is read only, but can be cleared by writing 1 to LIN_RX_F.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_OVER_F : RX Overflow Error Status Flag This bit is set when RX-FIFO overflow. If the number of bytes of received data is greater than RX-FIFO (UART_RBR) size, 16 bytes of UART0/UART1, this bit will be set. Note: This bit can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_EMPTY_F : Receiver FIFO Empty (Read Only)\nThis bit initiate RX-FIFO empty or not.\nWhen the last byte of RX-FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_FULL_F : Receiver FIFO Full (Read Only)\nThis bit initiates RX-FIFO full or not.\nThis bit is set when RX_POINTER_F is equal to 16, otherwise is cleared by hardware.\n
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PE_F : Parity Error State Status Flag This bit is set to logic 1 whenever the received character does not have a valid parity bit , and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FE_F : Framing Error Status Flag This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as a logic 0 ), and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BI_F : Break Status Flag This bit is set to a logic 1 whenever the received data input(RX) is held in the spacing state (logic 0 ) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits) and it is reset whenever the CPU writes 1 to this bit. Note: This bit can be cleared by writing 1 to it.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_OVER_F : TX Overflow Error Interrupt Status Flag If TX-FIFO (UART_THR) is full, an additional write to UART_THR will cause this bit to logic 1 . Note: This bit can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_EMPTY_F : Transmitter FIFO Empty (Read Only) This bit indicates TX-FIFO empty or not. When the last byte of TX-FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into THR (TX-FIFO not empty).
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TX_FULL_F : Transmitter FIFO Full (Read Only) This bit indicates TX-FIFO full or not. This bit is set when TX_POINTER_F is equal to 16, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TE_F : Transmitter Empty Status Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UA_THR) is empty and the STOP bit of the last byte has been transmitted. \nThis bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.\n
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RX_POINTER_F : RX-FIFO Pointer (Read Only)\nThis field indicates the RX-FIFO Buffer Pointer. When UART receives one byte from external device, RX_POINTER_F increases one. When one byte of RX-FIFO is read by CPU, RX_POINTER_F decreases one.
bits : 16 - 20 (5 bit)
access : read-only

TX_POINTER_F : TX-FIFO Pointer (Read Only)\nThis field indicates the TX-FIFO Buffer Pointer. When CPU writes one byte data into UART_THR, TX_POINTER_F increases one. When one byte of TX-FIFO is transferred to Transmitter Shift Register, TX_POINTER_F decreases one.
bits : 24 - 28 (5 bit)
access : read-only

LEV_RTS : RTSn Trigger Level \n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_ST : RTSn Pin State (Read Only)\nThis bit is the pin status of RTSn.\n
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LEV_CTS : CTSn Trigger Level\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTS_ST : CTSn Pin Status (Read Only)\nThis bit is the pin status of CTSn.\n
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DCT_F : Detect CTSn State Change Status Flag (Read Only) This bit is set whenever CTSn input has change state, and it will generate Modem interrupt to CPU when Modem_IEN (UART_IER [3]). Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-Out Comparator The time-out counter resets and starts counting whenever the RX-FIFO receives a new data word. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 bit data + parity bit + stop bit, so although software can configure this field by any value but it is recommend to filled this field great than 0xA.
bits : 0 - 8 (9 bit)
access : read-write

DLY : TX Delay Time Value This field is use to programming the transfer delay time between the last stop bit and next start bit. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3: The counting clock is baud rate clock.
bits : 16 - 23 (8 bit)
access : read-write

BRD : Baud Rate Divider \n
bits : 0 - 15 (16 bit)
access : read-write

DIV_16_EN : Divider 16 Enable\nNote: In IrDA mode, this bit must disable.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_SELECT : TX_SELECT\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_TX : INV_TX\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

INV_RX : INV_RX\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_BCNT : LIN TX Break Field Count Register\nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is LIN_TX_BCNT + 8.
bits : 0 - 2 (3 bit)
access : read-write

LIN_HEAD_SEL : LIN Header Selection\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_RX_EN : LIN RX Enable\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (INT_LIN)\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_TX_EN : LIN TX Header Trigger Enable\nNote2: If user wants to receive transmit data, it recommended to enable LIN_RX_EN bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BIT_ERR_EN : Bit Error Detect Enable\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_NMM : RS-485 Normal Multi-Drop Operation Mode (RS-485 NMM Mode)\n
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_AAD : RS-485 Auto Address Detection Operation Mode (RS-485 AAD Mode)\n
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_AUD : RS-485 Auto Direction Mode (RS-485 AUD Mode)\n
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS_485_ADD_EN : RS-485 Address Detection Enable\nThis bit is used to enable RS-485 hardware address detection mode.\n
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDR_PID_MATCH : Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (ADDR_PID_MATCH [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).
bits : 24 - 31 (8 bit)
access : read-write

FUN_SEL : Function Select Enable\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_RST : RX Software Reset\nWhen RX_RST is set, all the bytes in the receiving FIFO and RX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART peripheral clock cycles.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_RST : TX Software Reset\nWhen TX_RST is set, all the bytes in the transmitting FIFO and TX internal state machine are cleared.\nNote: This bit will auto clear and takes at least 3 UART engine clock cycles.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_DIS : Receiver Disable Register Note1: In RS-485 NMM mode, user can setting this bit to receive data or not that before detect address byte. Note2: In RS-485 NMM mode, this bit will be setting to 1 automatically. Note3: In RS-485 AAD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_DIS : Transfer Disable Register\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_RTS_EN : RTSn Auto-Flow Control Enable \nWhen RTSn auto-flow is enabled, if the number of bytes in the RX-FIFO equals the RTS_TRI_LEV (UART_TLCTL[13:12]), the UART will reassert RTSn signal.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

AUTO_CTS_EN : CTSn Auto-Flow Control Enable \n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_RX_EN : RX DMA Enable Note: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]), Frame Error Flag FE_F(UART_FSR[5]) or Parity Error Flag PE_F(UART_FSR[4]) , UART PDMA receive request operation is stop. Clear Break Error Flag BI_F or Frame Error Flag FE_F or Parity Error Flag PE_F by writing 1 to corresponding BI_F, FE_F and PE_F to make UART PDMA receive request operation continue.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DMA_TX_EN : TX DMA Enable Note: If RLS_IE (UART_IER[2]) is enabled and RLS_IS(UART_ISR[2]) is set to 1, the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break Error Flag BI_F(UART_FSR[6]), Frame Error Flag FE_F(UART_FSR[5]) or Parity Error Flag PE_F(UART_FSR[4]) , UART PDMA transmit request operation is stop. Clear Break Error Flag BI_F or Frame Error Flag FE_F or Parity Error Flag PE_F by writing 1 to corresponding BI_F, FE_F and PE_F to make UART PDMA transmit request operation continue.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_CTS_EN : CTSn Wake-Up Function Enable \n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_DATA_EN : Incoming Data Wake-Up Function Enable Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_EN : Auto-Baud Rate Detect Enable\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (INT_ABAUD) will be generated (If ABAUD_IE (UART_IER [7]) be enabled).
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATA_LEN : Data Length\n
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number Of STOP Bit Length\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity Enable\nNote: This bit has effect only when PBE bit (parity bit enable) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Stick Parity Enable Control Note1: When bits PBE, EPE and SPE are set, the parity bit is transmitted and checked as 0 . When PBE and SPE are set and EPE is cleared, the parity bit is transmitted and checked as 1 . Note2: In RS-485 mode, PBE, EPE and SPE can control bit 9, the bit 9 setting are shown as follows.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit When this bit is set to logic 1 , the serial data output (TX) is forced to the Spacing State (logic 0 ). This bit acts only on TX pin and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX-FIFO Interrupt (INT_RDA) Trigger Level When the number of bytes in the receiving FIFO equals to the RFITL then the RDA_IF will be set (if RDA_IEN (IER [0]) is enabled, an interrupt will be generated) Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 .
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTS_TRI_LEV : RTSn Trigger Level (For Auto-Flow Control Use)\nNote: This field is used for auto RTSn flow control.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDA_IE : Receive Data Available Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THRE_IE : Transmit Holding Register Empty Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLS_IE : Receive Line Status Interrupt Enable \n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEM_IE : Modem Status Interrupt Enable \n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTO_IE : RX Time-Out Interrupt Enable\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUF_ERR_IE : Buffer Error Interrupt Enable\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WAKE_IE : Wake-Up Interrupt Enable\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABAUD_IE : Auto-Baud Rate Interrupt Enable\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LIN_IE : LIN Interrupt Enable\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.