\n

I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x28 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected

Registers

I2CON

I2CTOUT

I2CDATA

I2CSADDR0

I2CSADDR1

I2CSAMASK0

I2CSAMASK1

I2CINTSTS

I2CSTATUS

I2CDIV


I2CON

I2C Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CON I2CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPEN ACK STOP START I2C_STS INTEN

IPEN : I2C Function Enable Control\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C function Disabled

#1 : 1

I2C function Enabled

End of enumeration elements list.

ACK : Assert Acknowledge Control Bit\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

When this bit is set to 0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse

#1 : 1

When this bit is set to 1 prior to address or data received, an acknowledged will be returned during the acknowledge clock pulse on the SCL line when (a). A slave is acknowledging the address sent from master. (b). The receiver devices are acknowledging the data sent by transmitter

End of enumeration elements list.

STOP : I2C STOP Control Bit In Master mode, set this bit to 1 to transmit a STOP condition to bus then the controller will check the bus condition if a STOP condition is detected and this bit will be cleared by hardware automatically. In Slave mode, set this bit to 1 to reset the controller to the defined not addressed Slave mode. This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#0 : 0

Will be cleared by hardware automatically if a STOP condition is detected

#1 : 1

Sends a STOP condition to bus in Master mode or reset the controller to not addressed in Slave mode

End of enumeration elements list.

START : I2C START Command\nSetting this bit to 1 to enter Master mode, the device sends a START or repeat START condition to bus when the bus is free and it will be cleared to 0 after the START command is active and the STATUS has been updated.\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

#0 : 0

After START or repeat START is active

#1 : 1

Sends a START or repeat START condition to bus

End of enumeration elements list.

I2C_STS : I2C Status\nWhen a new state is present in the I2CSTATUS register, if the INTEN bit is set, the I2C interrupt is requested. It must write one by software to this bit after the I2CINTSTS[0] is set to 1 and the I2C protocol function will go ahead until the STOP is active or the IPEN is disabled.\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C's Status disabled and the I2C protocol function will go ahead

#1 : 1

I2C's Status active

End of enumeration elements list.

INTEN : Interrupt Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#0 : 0

I2C interrupt Disabled

#1 : 1

I2C interrupt Enabled

End of enumeration elements list.


I2CTOUT

I2C Time Out Counter Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CTOUT I2CTOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOUTEN DIV4

TOUTEN : Time-Out Counter Enable/Disable Control\nWhen set this bit to enable, the 14 bits time-out counter will start counting when INTSTS (I2CINTSTS[0]) is cleared. Setting flag STAINTSTS to high or the falling edge of I2C clock or stop signal will reset counter and re-start up counting after INTSTS is cleared.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.

DIV4 : Time-Out Counter Input Clock Divider By 4 \nWhen Enabled, the time-out period is extended 4 times.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

Disabled

#1 : 1

Enabled

End of enumeration elements list.


I2CDATA

I2C DATA Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CDATA I2CDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : I2C Data Bits\nThe DATA contains a byte of serial data to be transmitted or a byte which has just been received. \nNote: Refer to Data register section for more detail information.
bits : 0 - 7 (8 bit)
access : read-write


I2CSADDR0

Slave Address Register 0
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSADDR0 I2CSADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GCALL SADDR

GCALL : General Call Function \nNote: Refer to Address Register section for more detail information..
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

General Call Function Disabled

#1 : 1

General Call Function Enabled

End of enumeration elements list.

SADDR : I2C Salve Address Bits\nThe content of this register is irrelevant when the device is in Master mode. In the Slave mode, the seven most significant bits must be loaded with the device's own address. The device will react if either of the address is matched.
bits : 1 - 7 (7 bit)
access : read-write


I2CSADDR1

Slave Address Register 1
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSADDR1 I2CSADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2CSAMASK0

Slave Address Mask Register 0
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSAMASK0 I2CSAMASK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAMASK

SAMASK : I2C Slave Address Mask Bits\n
bits : 1 - 7 (7 bit)
access : read-write

Enumeration:

0 : 0

Mask disable (the received corresponding register bit should be exact the same as address register)

1 : 1

Mask enable (the received corresponding address bit is don't care).

End of enumeration elements list.


I2CSAMASK1

Slave Address Mask Register 1
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CSAMASK1 I2CSAMASK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2CINTSTS

I2C Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CINTSTS I2CINTSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTSTS TIF

INTSTS : I2C STATUS's Interrupt Status\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#0 : 0

No bus event occurred

#1 : 1

New state is presented in the I2CSTATUS. Software can write 1 to cleat this bit

End of enumeration elements list.

TIF : Time-Out Status\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

#0 : 0

No Time-out flag. Software can cleat this flag

#1 : 1

Time-Out flag active and it is set by hardware. It can interrupt CPU when INTEN bit is set

End of enumeration elements list.


I2CSTATUS

I2C Status Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

I2CSTATUS I2CSTATUS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS

STATUS : I2C Status Bits (Read Only)\nIndicates the current status code of the bus information. The detail information about the status is described in the sections of I2C protocol register and operation mode.
bits : 0 - 7 (8 bit)
access : read-only


I2CDIV

I2C Clock Divided Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2CDIV I2CDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_DIV

CLK_DIV : I2C Clock Divided Bits\nNote: the minimum value of CLK_DIV is 4.
bits : 0 - 7 (8 bit)
access : read-write



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