Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x34 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
SPI Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GO_BUSY : Go And Busy Status
During the data transfer, this bit keeps the value of '1'. As the transfer is finished, this bit will be cleared automatically.
Note 1: All registers should be set before writing 1 to the GO_BUSY bit in the SPI_CTL register.
Note 2: In FIFO mode, this bit will be controlled by hardware. Software should not modify this bit..
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing this bit 0 to stop data transfer if SPI is transferring
#1 : 1
In Master mode, writing 1 to this bit to start the SPI data transfer In Slave mode, writing '1' to this bit indicates that the salve is ready to communicate with a master
End of enumeration elements list.
RX_NEG : Receive At Negative Edge\nNote: Refer to Edge Condition section.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The received data is latched at the rising edge of SPICLK
#1 : 1
The received data is latched at the falling edge of SPICLK
End of enumeration elements list.
TX_NEG : Transmit At Negative Edge\nNote: Refer to Edge Condition section.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transmitted data output is changed at the rising edge of SPICLK
#1 : 1
The transmitted data output is changed at the falling edge of SPICLK
End of enumeration elements list.
TX_BIT_LEN : Transmit Bit Length\n
bits : 3 - 7 (5 bit)
access : read-write
TX_NUM : Number Of Transmit/Receive Transaction\n
bits : 8 - 9 (2 bit)
access : read-write
LSB : Send LSB First\nNote: Refer to LSB First section.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The MSB, which bit of transmit/receive register depends on the setting of TX_BIT_LEN, is transmitted/received first
#1 : 1
The LSB, bit 0 of the SPI_TX0/1, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the SPI_RX register (SPI_RX0/1)
End of enumeration elements list.
CLKP : Clock Polarity\nNote: Refer to Clock Parity section.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The default level of SPICLK is low
#1 : 1
The default level of SPICLK is high
End of enumeration elements list.
SP_CYCLE : Suspend Interval (Master Only)\n
bits : 12 - 15 (4 bit)
access : read-write
INTEN : Interrupt Enable\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI Interrupt Disabled
#1 : 1
SPI Interrupt Enabled
End of enumeration elements list.
SLAVE : Slave Mode Indication\nNote: Refer to Slave Selection section
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI controller is set as Master mode
#1 : 1
SPI controller is set as Slave mode
End of enumeration elements list.
REORDER : Reorder Mode Selection\nNote: The suspend interval is defined in SP_CYCLE
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable both byte reorder and suspend functions
#01 : 1
Enable byte reorder function and insert a byte suspend interval among each byte. The setting of TX_BIT_LEN must be configured as 00b (32 bits/ word)
#10 : 2
Enable byte reorder function, but disable byte suspend function
#11 : 3
Disable byte reorder function, but insert a suspend interval among each byte. The setting of TX_BIT_LEN must be configured as 00b (32 bits/ word)
End of enumeration elements list.
FIFOM : FIFO Mode Enable\nNote: Refer to Dual FIFO Mode section.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
FIFO mode Disabled (in Normal mode)
#1 : 1
FIFO mode Enabled
End of enumeration elements list.
TWOB : 2 Data Channel Transfer Mode Active\nNote: When enabling TWOB, the setting of TX_NUM must be programmed as 00.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
2data channel transfer mode Disabled
#1 : 1
2data channel transfer mode Enabled
End of enumeration elements list.
VARCLK_EN : Variable Clock Enable\nNote: Refer to Variable Serial Clock Frequency section.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The serial clock output frequency is fixed and only decided by the value of DIVIDER1
#1 : 1
The serial clock output frequency is variable. The output frequency is decided by the value of VARCLK (SPI_VARCLK), DIVIDER1 and DIVIDER2
End of enumeration elements list.
WKEUP_EN : Wake-Up Enable\nNote: When the system enters the power-down mode, the system can be wake-up from the SPI controller when this bit is enabled and if there is any toggle in the SPICLK port. After the system wake-up, this bit must be clear by user to disable the wake-up requirement.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled when the system enters the power-down mode
#1 : 1
Wake-up function Enabled
End of enumeration elements list.
SPI Receive Data FIFO Register 0
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Receive Data FIFO Register\nThe received data can be read on it. If the FIFOM bit is set as 1, the user also checks the RX_EMPTY (SPI_STATUS[0]) to check if there is any more received data or not.\nNote 1: The SPI_RX1 is used only in TWOB bit (SPI_CTL[22]) is set 1. The first channel's received data shall be read from SPI_RX0 and the second channel's received data shall be read from SPI_RX1 in two-bit mode. SPI_RX0 shall be read first in TWOB mode.\nNote 2: These two registers are read only.
bits : 0 - 31 (32 bit)
access : read-only
SPI Receive Data FIFO Register 1
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI Transmit Data FIFO Register 0
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data FIFO Register\nThe Data Transmit Registers hold the data to be transmitted in the next transfer. The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.\nFor example, if TX_BIT_LEN is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer. If TX_BIT_LEN is set to 0x0, the SPI controller will perform a 32-bit transfer.\nNote: The SPI_TX1 is used only in TWOB bit (SPI_CTL[22]) is set 1. The first channel's transmitted data shall be written into SPI_TX0 and the second channel's transmitted data shall be written into SPI_TX1 in twodata channel mode. SPI_TX0 shall be written first in TWOB mode.
bits : 0 - 31 (32 bit)
access : write-only
SPI Transmit Data FIFO Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI Variable Clock Pattern Flag Register
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARCLK : Variable Clock Pattern Flag\nThe value in this field is the frequency patterns of the SPICLK.\n
bits : 0 - 31 (32 bit)
access : read-write
SPI PDMA Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_DMA_EN : Transmit PDMA Enable (PDMA Writes Data To SPI)\nNote 1: Refer to DMA section for more detail information.\nNote 2: Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.\nNote 3: If the 2 data channel function is enabled, the requirement timing shall append 18 APB clock based on the above clock period.\nNote 4: Hardware will clear this bit to 0 automatically after PDMA transfer done.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmit PDMA function Disabled
#1 : 1
Transmit PDMA function Enabled
End of enumeration elements list.
RX_DMA_EN : Receiver PDMA Enable (PDMA Reads SPI Data To Memory)
Note 1: Refer to DMA section for more detail information.
Note 2: Hardware will clear this bit to 0 automatically after PDMA transfer done.
Note 3: In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clocks + 4 APB clocks.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Receiver PDMA function Disabled
#1 : 1
Receiver PDMA function Enabled
End of enumeration elements list.
PDMA_RST : PDMA Reset
It is used to reset the SPI PDMA function into default state.
Note: It is auto cleared to 0 after the reset function done.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
After reset PDMA function or in normal operation
#1 : 1
Reset PDMA function
End of enumeration elements list.
SPI FIFO Counter Clear Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_CLR : Receiving FIFO Counter Clear
Note: This bit is used to clear the receiver counter in FIFO Mode. This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter. After the clear operation, the flag of RX_EMPTY in SPI_STATUS[0] will be set to 1 .
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No clear the received FIFO
#1 : 1
Clear the received FIFO
End of enumeration elements list.
TX_CLR : Transmitting FIFO Counter Clear
Note: This bit is used to clear the transmit counter in FIFO Mode. This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter. After the clear operation, the flag of TX_EMPTY in SPI_STATUS[2] will be set to 1 .
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No clear the transmitted FIFO
#1 : 1
Clear the transmitted FIFO
End of enumeration elements list.
SPI Status Register
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_EMPTY : Received Dual FIFO_EMPTY Status\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data FIFO is not empty in the dual FIFO mode
#1 : 1
Received data FIFO is empty in the dual FIFO mode
End of enumeration elements list.
RX_FULL : Received Dual FIFO_FULL Status\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Received data FIFO is not full in dual FIFO mode
#1 : 1
Received data FIFO is full in the dual FIFO mode
End of enumeration elements list.
TX_EMPTY : Transmitted Dual FIFO_EMPTY Status\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data FIFO is not empty in the dual FIFO mode
#1 : 1
Transmitted data FIFO is empty in the dual FIFO mode
End of enumeration elements list.
TX_FULL : Transmitted Dual FIFO_FULL Status\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transmitted data FIFO is not full in the dual FIFO mode
#1 : 1
Transmitted data FIFO is full in the dual FIFO mode
End of enumeration elements list.
LTRIG_FLAG : Level Trigger Flag (INTERNAL ONLY)\nIn Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.\nNote: This bit is read only
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The transferred bit length of one transaction does not meet the specified requirement
#1 : 1
The transferred bit length meets the specified requirement which defined in TX_BIT_LEN
End of enumeration elements list.
SLV_START_INTSTS : Slave Start Interrupt Status\nIt is used to indicate that the transfer has started in Slave mode with no slave select.\n
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Slave started transfer no active
#1 : 1
Transfer has started in Slave mode with no slave select. It is auto clear by transfer done or writing one clear
End of enumeration elements list.
INTSTS : Interrupt Status
Note: This bit is read only, but can be cleared by writing 1 to this bit.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer is not finished yet
#1 : 1
Transfer is done. The interrupt is requested when the INTEN (SPI_CTL[17]) bit is enabled
End of enumeration elements list.
SPI Clock Divider Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVIDER1 : Clock Divider 1 Register \nThe value is the 1th frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/\n\nNote 1: The DIVIDER1 can be set as 0. If the DIVIDER1 is set as zero, the frequency of SPI_SCLK is the same as PCLK in Master mode.\nNote 2: In Slave mode, the period of SPI clock driven by a master shall equal to or over 5 times the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of the frequency of slave's PCLK.
bits : 0 - 15 (16 bit)
access : read-write
DIVIDER2 : Clock Divider 2 Register \nThe value is the 2nd 2nd frequency divider of the PCLK to generate the serial clock of SPICLK. The desired frequency is obtained according to the following equation:\n/
bits : 16 - 31 (16 bit)
access : read-write
SPI Slave Select Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSR : Slave Select Active Register (Master Only)
If AUTOSS bit (SPI_SSR[3]) is cleared, writing 1 to SSR[0] bit sets the SPISS[0] line to an active state and writing 0 sets the line back to inactive state.( the same as SSR[1] for SPISS[1])
Note 1: This interface can only drive one device/slave at a given time. Therefore, the slave select of the selected device must be set to its active level before starting any read or write transfer.
Note 2: SPISS[0] is also defined as device/slave select input in Slave mode. And that the slave select input must be driven by edge active trigger which level depend on the SS_LVL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Both SPISS[1] and SPISS[0] are inactive
#01 : 1
SPISS[1] is inactive, SPISS[0] is active.\nSPISS[1] is inactive, SPISS[0] is active on the duration of transaction
#10 : 2
SPISS[1] is active, SPISS[0] is inactive.\nSPISS[1] is active on the duration of transaction, SPISS[0] is inactive
#11 : 3
Both SPISS[1] and SPISS[0] are active.\nBoth SPISS[1] and SPISS[0] are active on the duration of transaction
End of enumeration elements list.
SS_LVL : Slave Select Active Level\nIt defines the active level of device/slave select signals (SPISS[1:0]).\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The SPISS slave select signal is active Low
#1 : 1
The SPISS slave select signal is active High
End of enumeration elements list.
AUTOSS : Automatic Slave Selection (Master Only)\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
If this bit is set as 0 , slave select signals are asserted and de-asserted by setting and clearing related bits in SSR[1:0] register
#1 : 1
If this bit is set as 1 , SPISS[1:0] signals are generated automatically. It means that device/slave select signal, which is set in SSR[1:0] register is asserted by the SPI controller when transmit/receive is started by setting the GO_BUSY bit, and is de-asserted after each transaction is done
End of enumeration elements list.
SS_LTRIG : Slave Select Level Trigger\n
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The input slave select signal is edge-trigger
#1 : 1
The slave select signal will be level-trigger. It depends on SS_LVL to decide the signal is active low or active high
End of enumeration elements list.
NOSLVSEL : No Slave Selected In Slave Mode
This is used to ignore the slave select signal in Slave mode. The SPI controller can work on 3 wire interface including SPICLK, SPI_MISO and SPI_MOSI when it is set as a slave device.
Note 1: Refer to No Slave Select Mode.
Note 2: In no slave select signal mode, the SS_LTRIG (SPI_SSR[4]) shall be set as 1 .
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The controller is 4-wire bi-direction interface
#1 : 1
The controller is 3-wire bi-direction interface in Slave mode. When this bit is set as 1, the controller start to transmit/receive data after the GO_BUSY bit active and the serial clock input
End of enumeration elements list.
SLV_ABORT : Abort In Slave Mode With No Slave Selected
Note 1:Refer to No Slave Select Mode.
Note 2: It is auto clear to 0 by hardware when the abort event is active.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No force the slave abort
#1 : 1
Force the current transfer done in no slave select mode
End of enumeration elements list.
SSTA_INTEN : Slave Start Interrupt Enable\nNote : Refer to No Slave Select Mode.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Transfer start interrupt Disabled in no slave select mode
#1 : 1
Transaction start interrupt Enabled in no slave select mode. It is cleared when the current transfer done or the SLV_START_INTSTS bit cleared (write 1 clear)
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.