I2S_CTRL (CTRL)

I2S_TXFIFO (TXFIFO)

I2S_RXFIFO (RXFIFO)

I2S_CLKDIV (CLKDIV)

I2S_INTEN (INTEN)

I2S_STATUS (STATUS)

I2SEN : I2S Controller Enable\n
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : Transmit Enable\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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RXEN : Receive Enable\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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MUTE : Transmitting Mute Enable\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

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WORDWIDTH : Word Width \nThis bit field indicates the bit-width of data word.\n
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

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MONO : Monaural Data Selection\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FORMAT : Data Format Selection\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

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SLAVE : Slave Mode Selection\nI2S can operate as master or Slave mode. For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and also outputs I2S_BCLK and I2S_LRCLK signals to the audio CODEC. When act as Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from the outer audio CODEC chip.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTH : Transmit FIFO Threshold Level\nIf remain data word (32 bits) in transmitting FIFO is the same or less than threshold level then TXTHF flag is set.\n
bits : 9 - 11 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTH : Receiving FIFO Threshold Level\nWhen received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.\n
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MCLKEN : Master Clock Enable\nEnable master MCLK timing output to the external audio codec device. The output frequency is according to MCLK_DIV[2:0] in the I2S_CLKDIV register.\n
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RCHZCEN : Right Channel Zero Cross Detect Enable If this bit is set to 1 , when right channel data sign bit is changed or next shift data bits are all zero then RZCF flag in I2S_STATUS register is set to 1 . It works on transmitting mode only.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LCHZCEN : Left Channel Zero Cross Detect Enable If this bit is set to 1 , when left channel data sign bit is changed or next shift data bits are all zero then LZCF flag in I2S_STATUS register is set to 1 . It works on transmitting mode only.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CLR_TXFIFO : Clear Transmit FIFO Write 1 to clear transmitting FIFO, internal pointer is reset to FIFO start point, TX_LEVEL[3:0] returns to zero and transmitting FIFO becomes empty but data in transmit FIFO is not changed. This bit is clear by hardware automatically, read it return zero.
bits : 18 - 18 (1 bit)
access : read-write

CLR_RXFIFO : Clear Receiving FIFO Write 1 to clear receiving FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns to zero and receiving FIFO becomes empty. This bit is cleared by hardware automatically, and read it return zero.
bits : 19 - 19 (1 bit)
access : read-write

TXDMA : Enable Transmit DMA\nWhen TX DMA is enabled, I2S requests PDMA to transfer data from memory to transmitting FIFO if FIFO is not full\n
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDMA : Enable Receive DMA\nWhen RX DMA is enabled, I2S requests PDMA to transfer data from receiving FIFO to memory if FIFO is not empty.\n
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFIFO : Transmitting FIFO Register\nI2S contains 8 words (8x32-bit) data buffer for data transmitting. Write data to this register in order to prepare data for transmitting. The remaining word number is indicated by TX_LEVEL[3:0] in the I2S_STATUS register. This register is write only.
bits : 0 - 31 (32 bit)
access : write-only

RXFIFO : Receiving FIFO Register\nI2S contains 8 words (8x32-bit) data buffer for data receiving. Read this register to get data in FIFO. The remaining data word number is indicated by RX_LEVEL[3:0] in the I2S_STATUS register. This register is read only.
bits : 0 - 31 (32 bit)
access : read-only

MCLK_DIV : Master Clock Divider If the external crystal frequency is (2xMCLK_DIV)*256fs then software can program these bits to generate 256fs clock frequency to audio CODEC chip. If MCLK_DIV is set to 0 , MCLK is the same as external clock input.
bits : 0 - 2 (3 bit)
access : read-write

BCLK_DIV : Bit Clock Divider\nIf I2S is operated in Master mode, bit clock is provided by this chip. Software can program these bits to generate sampling rate clock frequency.\n
bits : 8 - 15 (8 bit)
access : read-write

RXUDFIE : Receiving FIFO Underflow Interrupt Enable Interrupt occurs if this bit is set to 1 and receiving FIFO underflow flag is set to 1 .
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVFIE : Receiving FIFO Overflow Interrupt Enable Interrupt occurs if this bit is set to 1 and receiving FIFO overflow flag is set to 1
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHIE : Receiving FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in receiving FIFO is less than RXTH[2:0].
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXUDFIE : Transmitting FIFO Underflow Interrupt Enable Interrupt occurs if this bit is set to 1 and transmitting FIFO underflow flag is set to 1 .
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVFIE : Transmitting FIFO Overflow Interrupt Enable Interrupt occurs if this bit is set to 1 and transmitting FIFO overflow flag is set to 1
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHIE : Transmitting FIFO Threshold Level Interrupt Enable Interrupt occurs if this bit is set to 1 and data words in transmitting FIFO is less than TXTH[2:0].
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RZCIE : Right Channel Zero Cross Interrupt Enable Interrupt occurs if this bit is set to 1 and right channel is zero crossing.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LZCIE : Left Channel Zero Cross Interrupt Enable Interrupt occurs if this bit is set to 1 and left channel is zero crossing.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

I2SINT : I2S Interrupt Flag\nNote: This bit is read only and it is wire-OR of I2STXINT and I2SRXINT bits.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

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I2SRXINT : I2S Receiving Interrupt\nNote: This bit is read only
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

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I2STXINT : I2S Transmit Interrupt\nNote: This bit is read only
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

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RIGHT : Right Channel\nThis bit indicates the current transmitting data is belong to right channel\nNote: This bit is read only
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXUDF : Receiving FIFO Underflow Flag Read the receiving FIFO when it is empty, this bit set to 1 indicate underflow occur. Note: This bit is cleared by writing 1.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOVF : Receiving FIFO Overflow Flag When the receiving FIFO is full and receiving hardware attempts to write data into receiving FIFO then this bit is set to 1 . Data in 1st buffer is overwritten. Note: This bit is cleared by writing 1.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTHF : Receiving FIFO Threshold Flag When data word(s) in the receiving FIFO is equal to or higher than threshold value set in RXTH[2:0], the RXTHF bit becomes to 1 . It keeps at 1 till RX_LEVEL[3:0] less than RXTH[1:0] after software reads data from the RXFIFO register. Note: This bit is read only
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXFULL : Receiving FIFO Full\nThis bit reflect data word number in the receiving FIFO is 8\nNote: This bit is read only
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXEMPTY : Receiving FIFO Empty\nThis bit reflect data word number in the receiving FIFO is zero\nNote: This bit is read only.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXUDF : Transmitting FIFO Underflow Flag When the transmitting FIFO is empty and shift logic hardware read data from the data FIFO causes this set to 1 . Note: This bit is cleared by writing 1.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOVF : Transmit FIFO Overflow Flag Write data to the transmitting FIFO when it is full and this bit will set to 1 Note: This bit is cleared by writing 1.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXTHF : Transmitting FIFO Threshold Flag When data word(s) in the transmitting FIFO is equal to or lower than threshold value set in TXTH[2:0],the TXTHF bit becomes to 1 . It keeps at 1 till TX_LEVEL[3:0] is higher than TXTH[1:0] after software writes data into the TXFIFO register. Note: This bit is read only
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXFULL : Transmitting FIFO Full\nThis bit reflect data word number in the transmitting FIFO is 8\nNote: This bit is read only
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEMPTY : Transmitting FIFO Empty\nThis bit reflect data word number in the transmitting FIFO is zero\nNote: This bit is read only.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXBUSY : Transmitting Busy\nThis bit is clear to 0 when all data in the transmitting FIFO and shift buffer is shifted out. Set this bit to 1 when 1st data is loading to shift buffer. \nNote: This bit is read only.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RZCF : Right Channel Zero Cross Flag \nIt indicates the data sign of right channel next sample data is changed or all data bits are zero.\nNote: This bit is cleared by writing 1.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LZCF : Left Channel Zero Cross Flag \nIt indicates the next sample data sign bit of left channel is changed or all data bits are zero.\nNote: This bit is cleared by writing 1.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RX_LEVEL : Receive FIFO Level\nThese bits indicate the number of data word(s) in the receiving FIFO.\n
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TX_LEVEL : Transmitting FIFO Level\nThese bits indicate the number of data word(s) in the transmitting FIFO.\n
bits : 28 - 31 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.