Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x70 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA4 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x50 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
USB Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_EN : USB Function Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB Disabled
#1 : 1
USB Enabled
End of enumeration elements list.
PHY_EN : PHY Transceiver Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PHY transceiver Disabled
#1 : 1
PHY transceiver Enabled
End of enumeration elements list.
PWRDB : Power Down PHY Transceiver, Low Active\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power-down related circuit of PHY transceiver
#1 : 1
Turn-on related circuit of PHY transceiver
End of enumeration elements list.
DPPU_EN : Pull-Up Resistor On USB_DP Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled the pull-up resistor in USB_DP bus
#1 : 1
Pull-up resistor in USB_DP bus will be active
End of enumeration elements list.
DRVSE0 : Force USB PHY Transceiver To Drive SE0 (Single Ended Zero)
The Single Ended Zero is present when both lines (USB_DP, USB_DM) are being pulled low.
The default value is 1 .
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
None
#1 : 1
Force USB PHY transceiver to drive SE0
End of enumeration elements list.
RWAKEUP : Remote Wake-Up\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Don't force USB bus to K state
#1 : 1
Force USB bus to K (USB_DP low, USB_DM: high) state, used for remote wake-up
End of enumeration elements list.
WAKEUP_EN : Wake-Up Function Enable\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB wake-up function Disabled
#1 : 1
USB wake-up function Enabled
End of enumeration elements list.
Device Function Address Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FADDR : USB device's function address
bits : 0 - 6 (7 bit)
access : read-write
Endpoint Status Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
OVERRUN : Overrun\nIt means the received data is over the maximum payload number or not.\n
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
No overrun
#1 : 1
Out Data more than the Max Payload in MXPLD register or the Setup Data more than 8 Bytes
End of enumeration elements list.
EPSTS0 : Endpoint 0 Bus Status\n
bits : 8 - 11 (4 bit)
access : read-only
EPSTS1 : Endpoint 1 Bus Status\n
bits : 12 - 15 (4 bit)
access : read-only
EPSTS2 : Endpoint 2 Bus Status\n
bits : 16 - 19 (4 bit)
access : read-only
EPSTS3 : Endpoint 3 Bus Status\n
bits : 20 - 23 (4 bit)
access : read-only
EPSTS4 : Endpoint 4 Bus Status\n
bits : 24 - 27 (4 bit)
access : read-only
EPSTS5 : Endpoint 5 Bus Status\n
bits : 28 - 31 (4 bit)
access : read-only
Setup Token Buffer Segmentation Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEG : None
bits : 3 - 8 (6 bit)
access : read-write
Endpoint 0 Buffer Segmentation Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFSEG : Refer to the section 5.4.3.3 for the endpoint SRAM structure and its description.
bits : 3 - 8 (6 bit)
access : read-write
Endpoint 0 Maximal Payload Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MXPLD : Maximal Payload
It is used to define the length of data which is transmitted to host (IN token) or the actual length of data receiving from host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1). When the register is written by CPU,
For IN token, the value of MXPLD is used to define the length of data to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from host and the value of MXPLD is the maximal data length comes from host.
(2). When the register is read by CPU,
For IN token, the value of MXPLD is indicated the length of data be transmitted to host
For OUT token, the value of MXPLD is indicated the actual length of data receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.
bits : 0 - 8 (9 bit)
access : read-write
Endpoint 0 Configuration Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EP_NUM : Endpoint Number\nThese bits are used to define the endpoint number of the current endpoint
bits : 0 - 3 (4 bit)
access : read-write
ISOCH : Isochronous Endpoint\nThis bit is used to set the endpoint as Isochronous endpoint, no handshake.
bits : 4 - 4 (1 bit)
access : read-write
EPMODE : Endpoint Mode\n
bits : 5 - 6 (2 bit)
access : read-write
DSQ_SYNC : Data Sequence Synchronization\nIt is used to specify the DATA0 or DATA1 PID in the current transaction. It will toggle automatically in IN token after host response ACK. In the other tokens, the user shall take care of it to confirm the right PID in its transaction.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DATA0 PID
#1 : 1
DATA1 PID
End of enumeration elements list.
CSTALL : Clear STALL Response\n
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled to the device to clear the STALL handshake in setup stage
#1 : 1
Clear the device to response STALL handshake in setup stage
End of enumeration elements list.
SSTALL : Set STALL Response\n
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled the device to response STALL
#1 : 1
Set the device to respond STALL automatically
End of enumeration elements list.
Endpoint 1 Buffer Segmentation Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Maximal Payload Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 1 Configuration Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB Bus Status Register
address_offset : 0x4 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
USBRST : USB Reset Status \n
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
#1 : 1
Bus reset when SE0 (single-ended 0) more than 2.5uS. It is read only
End of enumeration elements list.
SUSPEND : Suspend Status \n
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#1 : 1
Bus idle more than 3mS, either cable is plugged off or host is sleeping. It is read only
End of enumeration elements list.
RESUME : Resume Status\n
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
#1 : 1
Resume from suspend. It is read only
End of enumeration elements list.
TIMEOUT : Time Out Flag\n
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
#1 : 1
Bus no any response more than 18 bits time. It is read only
End of enumeration elements list.
FLDET : Device Floating Detection\n
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
#0 : 0
The controller didn't attach into the USB
#1 : 1
When the controller is attached into the USB, this bit will be set as 1
End of enumeration elements list.
Endpoint 2 Buffer Segmentation Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Maximal Payload Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 2 Configuration Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Buffer Segmentation Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Maximal Payload Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 3 Configuration Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Buffer Segmentation Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Maximal Payload Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 4 Configuration Register
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Buffer Segmentation Register
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Maximal Payload Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Endpoint 5 Configuration Register
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUSEVT_IE : Bus Event Interrupt Enable\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
BUS event interrupt Disabled
#1 : 1
BUS event interrupt Enabled
End of enumeration elements list.
USBEVT_IE : USB Event Interrupt Enable\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
USB event interrupt Disabled
#1 : 1
USB event interrupt Enabled
End of enumeration elements list.
FLDET_IE : Floating Detect Interrupt Enable\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Floating detect Interrupt Disabled
#1 : 1
Floating detect Interrupt Enabled
End of enumeration elements list.
WAKEUP_IE : USB Wake-Up Interrupt Enable\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up Interrupt Disabled
#1 : 1
Wake-up Interrupt Enabled
End of enumeration elements list.
USB PDMA Control Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDMA_RW : PDMA_RW\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PDMA will read data from memory to USB buffer
#1 : 1
The PDMA will read data from USB buffer to memory
End of enumeration elements list.
PDMA_TRG : Active PDMA Function\nThis bit will be automatically cleared after PDMA transfer done.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The PDMA function is not active
#1 : 1
The PDMA function in USB is active
End of enumeration elements list.
BYTEM : CPU Access USB SRAM Size Mode Select\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Word Mode: The size of the transfer from CPU to USB SRAM is Word order
#1 : 1
Byte Mode: The size of the transfer from CPU to USB SRAM is Byte order
End of enumeration elements list.
PDMA_RST : PDMA Reset\nIt is used to reset the USB PDMA function into default state. \nNote: it is auto clear to 0 after the reset function done.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Reset PDMA Reset Disable
#1 : 1
Reset the PDMA function in this controller
End of enumeration elements list.
Interrupt Event Status Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_STS : BUS Interrupt Status\nThe BUS event means there is bus suspense or bus resume in the bus. This bit is used to indicate that there is one of events in the bus.\n
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No BUS event is occurred
#1 : 1
BUS event occurred check USB_BUSSTS [3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS [0]
End of enumeration elements list.
USB_STS : USB Interrupt Status\nThe USB event means that there is Setup Token, IN token, OUT ACK, ISO IN, or ISO OUT event in the bus. This bit is used to indicate that there is one of events in the bus.\n
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No USB event is occurred
#1 : 1
USB event occurred, check EPSTS0~5[3:0] in USB_EPSTS [31:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [1] or USB_INTSTS[31] or EPEVT0~5
End of enumeration elements list.
FLD_STS : Floating Interrupt Status\n
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
There is not attached event in the USB
#1 : 1
There is attached event in the USB and it is cleared by write 1 to USB_INTSTS [2]
End of enumeration elements list.
WKEUP_STS : Wake-Up Interrupt Status\n
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No wake-up event is occurred
#1 : 1
Wake-up event occurred, cleared by write 1 to USB_INTSTS [3]
End of enumeration elements list.
EPEVT0 : USB Event Status On EP0\n
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in Endpoint 0
#1 : 1
USB event occurred on Endpoint 0, check USB_EPSTS[11:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [16] or USB_INTSTS [1]
End of enumeration elements list.
EPEVT1 : USB Event Status On EP1\n
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in Endpoint 1
#1 : 1
USB event occurred on Endpoint 1, check USB_EPSTS[15:12] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [17] or USB_INTSTS [1]
End of enumeration elements list.
EPEVT2 : USB Event Status On EP2\n
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in Endpoint 2
#1 : 1
USB event occurred on Endpoint 2, check USB_EPSTS[19:16] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [18] or USB_INTSTS [1]
End of enumeration elements list.
EPEVT3 : USB Event Status On EP3\n
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in Endpoint 3
#1 : 1
USB event occurred on Endpoint 3, check USB_EPSTS[23:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [19] or USB_INTSTS [1]
End of enumeration elements list.
EPEVT4 : USB Event Status On EP4\n
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in Endpoint 4
#1 : 1
USB event occurred on Endpoint 4, check USB_EPSTS[27:24] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [20] or USB_INTSTS [1]
End of enumeration elements list.
EPEVT5 : USB Event Status On EP5\n
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
No event occurred in Endpoint 5
#1 : 1
USB event occurred on Endpoint 5, check USB_EPSTS[31:28] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS [21] or USB_INTSTS [1]
End of enumeration elements list.
SETUP : Setup Event Status \n
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
No Setup event
#1 : 1
Setup event occurred, cleared by write 1 to USB_INTSTS[31]
End of enumeration elements list.
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