ADC_RESULT0 (RESULT0)

ADC_RESULT4 (RESULT4)

ADC_RESULT5 (RESULT5)

ADC_RESULT6 (RESULT6)

ADC_RESULT7 (RESULT7)

ADC_RESULT10 (RESULT10)

ADCR

ADCHER

ADCMPR0

ADCMPR1

ADC_RESULT1 (RESULT1)

ADSR

ADFCR

ADPDMA

ADCDELSEL

ADC_RESULT2 (RESULT2)

ADC_RESULT3 (RESULT3)

RSLT : A/D Conversion Result\nThis field contains 12 bits conversion result.
bits : 0 - 11 (12 bit)
access : read-only

ADEN : A/D Converter Enable\nBefore starting A/D conversion function, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADIE : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADMD : A/D Converter Operation Mode\n
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGS : Hardware Trigger Source\nSoftware should disable TRGE and ADST before change TRGS. \nIn hardware trigger mode, the ADST bit is set by the external trigger from STADC, However software has the highest priority to set or cleared ADST bit at any time.
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGCOND : External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state.\n
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRGEN : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.\n
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PTEN : PDMA Transfer Enable\n
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADST : A/D Conversion Start\nADST bit can be set to 1 from two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.\nNote: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMSEL : Select A/D Enable Time-Out Source \n
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TMTRGMOD : Timer Event Trigger ADC Conversion\nsetting TMSEL to select timer event from timer0~3
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

REFSEL : Reference Voltage Source Selection\n
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN0 : Analog Input Channel 0 Enable Control\nIf more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN1 : Analog Input Channel 1 Enable Control\n
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN2 : Analog Input Channel 2 Enable Control\n
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN3 : Analog Input Channel 3 Enable Control\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN4 : Analog Input Channel 4 Enable Control\n
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN5 : Analog Input Channel 5 Enable Control\n
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN6 : Anaslog Input Channel 6 Enable Control\n
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN7 : Analog Input Channel 7 Enable Control\n
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHEN10 : Analog Input Channel 10 Enable Control\n
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CH10SEL : Select Channel10 Input\n
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPEN : Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1, and CMPMATCNT is 0, the CMPF (ADSR[2,1]) will be set once the match is hit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF (ADSR[2,1]) will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCOND : Compare Condition Note: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF (ADSR[2,1]) will be set.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPCH : Compare Channel Selection\nSet this field to select which channel's result to be compared.\nNote: Valid setting of this field is channel 0~10.
bits : 3 - 6 (4 bit)
access : read-write

CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 8 - 11 (4 bit)
access : read-write

CMPD : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
bits : 18 - 27 (10 bit)
access : read-write

ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nThis flag can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write

CMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUSY : BUSY/IDLE\n
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHANNEL : Current Conversion Channel (Read Only)\n
bits : 4 - 7 (4 bit)
access : read-only

VALID15_8 : Data Valid Flag\nAfter ADC converts finish, this field will set to high.\nThis field will clear when ADC_RESULTx be read.\nNote: Those flags are for ADC_RESULT0~7
bits : 8 - 15 (8 bit)
access : read-write

VALID18 : Data Valid Flag\nAfter ADC converts finish, this field will set to high.\nThis field will clear when ADC_RESULTx be read.\nNote: This flag is for ADC_RESULT10
bits : 18 - 18 (1 bit)
access : read-write

OVERRUN27_24 : Over Run Flag\nWhen VALID is high and ADC converts finish, this field will set to high.\nNote: Those flag are for ADC_RESULT0~7
bits : 20 - 27 (8 bit)
access : read-write

OVERRUN30 : Over Run Flag\nWhen VALID is high and ADC converts finish, this field will set to high.\nNote: This flag is for ADC_RESULT10
bits : 30 - 30 (1 bit)
access : read-write

AD_PDMA : ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.
bits : 0 - 11 (12 bit)
access : read-only

En2StDelay : A/D Delay Time Select Register\nSet this register to adjust the time interval (in PCLK unit )between start signal and enable signal of ADC\nNote: The time interval is En2StDelay+1 PCLK cycle
bits : 0 - 7 (8 bit)
access : read-write

TMPDMACNT : PDMA Count\nWhen each time out event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set, ADC will not be enabled and start transfer even though the time out event occur
bits : 8 - 15 (8 bit)
access : read-write

ADCSTHOLDCNT : ADC Start Hold Time Counter\nThis ADC start is the start signal from ADC controller to analog ADC, not the ADST in ADCR[11],.\nIn Figure 517, when ADC start signal transition from high to low, the ADC reset signal will transition from low to high, at this moment the ADC hold the input analog single and stop holding when ADC start signal transition from low to high.\nThe interval of the holding time is programmable by setting this register. ADC need ADC start signal to keep low level at least 2 ADC CLOCK in order to get converting result more accurately. Setting this register will change the interval in ADC CLOCK unit
bits : 16 - 23 (8 bit)
access : read-write