\n
address_offset : 0x0 Bytes (0x0)
size : 0x5C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
A/D Data Register 0
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RSLT : A/D Conversion Result\nThis field contains 12 bits conversion results.
bits : 0 - 11 (12 bit)
access : read-only
VALID : Data Valid Flag\nIt is a mirror of VALID bit in ADC_RESULTx
bits : 16 - 16 (1 bit)
access : read-only
OVERRUN : Over Run Flag\nIt is a mirror to OVERRUN bit in ADC_RESULTx
bits : 17 - 17 (1 bit)
access : read-only
Reserve : Reserved
bits : 18 - 31 (14 bit)
access : read-only
A/D Data Register 4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 8
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 9
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 10
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 11
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 12
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 13
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 14
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 15
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 16
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 17
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Control Register
address_offset : 0x48 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADEN : A/D Converter Enable\nBefore starting A/D conversion, this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit power consumption.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
ADIE : A/D Interrupt Enable\nA/D conversion end interrupt request is generated if ADIE bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D interrupt function Disabled
#1 : 1
A/D interrupt function Enabled
End of enumeration elements list.
ADMD : A/D Converter Operation Mode\n
bits : 2 - 3 (2 bit)
access : read-write
TRGS : Hardware Trigger Source\n
bits : 4 - 5 (2 bit)
access : read-write
TRGCOND : External Trigger Condition
bits : 6 - 7 (2 bit)
access : read-write
TRGE : External Trigger Enable\nEnable or disable triggering of A/D conversion by external STADC pin.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled,
#1 : 1
Enabled,
End of enumeration elements list.
PTEN : PDMA Transfer Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA data transfer Disabled
#1 : 1
PDMA data transfer in ADC_RESULT 0~17 Enabled
End of enumeration elements list.
DIFF : Differential Mode Selection\n1:ADC is operated in differential mode\n0:ADC is operated in single-ended mode\nNote: Calibration should calibrated each time when switching between single-ended and differential mode
bits : 10 - 10 (1 bit)
access : read-write
ADST : A/D Conversion Start\nADST bit can be set to 1 from two sources: software write and external pin STADC. ADST is cleared to 0 by hardware automatically at the end of single mode and single-cycle scan mode on specified channels. In continuous scan mode, A/D conversion is continuously performed sequentially unless software writes 0 to this bit or chip reset.\nNote: After ADC conversion done, SW needs to wait at least one ADC clock before to set this bit high again.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion stopped and A/D converter enter idle state
#1 : 1
Conversion starts
End of enumeration elements list.
TMSEL : Select A/D Enable Time-out Source
bits : 12 - 13 (2 bit)
access : read-write
TMTRGMOD : Timer Event Trigger ADC Conversion
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
This function Disabled
#1 : 1
ADC Enabled by TIMER OUT event
End of enumeration elements list.
REFSEL : Reference Voltage Source Selection
bits : 16 - 17 (2 bit)
access : read-write
RESSEL : Resolution Selection
bits : 18 - 19 (2 bit)
access : read-write
TMPDMACNT : PDMA Count\nWhen each timer event occur PDMA will transfer TMPDMACNT +1 ADC result in the amount of this register setting\nNote: The total amount of PDMA transferring data should be set in PDMA byte count register. When PDMA finish is set, ADC will not be enabled and start transfer even though the timer event occurred
bits : 24 - 31 (8 bit)
access : read-write
A/D Channel Enable Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHEN0 : Analog Input Channel 0 Enable (Convert Input Voltage from PA.0 )\nIf more than one channel in single mode is enabled by software, the least channel is converted and other enabled channels will be ignored.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN1 : Analog Input Channel 1 Enable(Convert input voltage from PA.1 )
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN2 : Analog Input Channel 2 Enable (Convert Input Voltage from PA.2 )
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN3 : Analog Input Channel 3 Enable(Convert input voltage from PA.3 )
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN4 : Analog Input Channel 4 Enable (Convert Input Voltage from PA.4 )
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN5 : Analog Input Channel 5 Enable (Convert Input Voltage from PA.5 )
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN6 : Anaslog Input Channel 6 Enable (Convert Input Voltage from PA.6 )
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN7 : Analog Input Channel 7 Enable (Convert Input Voltage from PA.7 )
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN8 : Analog Input Channel 8 Enable for DAC0 (Convert Input Voltage from PD.0 )
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN9 : Analog Input Channel 9 Enable for DAC1 (Convert Input Voltage from PD.1 )
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN10 : Analog Input Channel 10 Enable (Convert Input Voltage from PD.2 )
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN11 : Analog Input Channel 11 Enable(Convert input voltage from PD.3 )
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN12 : Analog Input Channel 12 Enable (Convert DAC0 Output Voltage)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN13 : Analog Input Channel 13 Enable (Convert DAC1 Output Voltage)
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN14 : Analog Input Channel 14 Enable (Convert VTEMP)
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN15 : Analog Input Channel 15 Enable (Convert Int_VREF)
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN16 : Analog Input Channel 16 Enable (Convert AVDD)
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
CHEN17 : Analog Input Channel 17 Enable (Convert AVSS)
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disabled
#1 : 1
Enabled
End of enumeration elements list.
A/D Compare Register 0
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Enable\nSet this bit to 1 to enable compare CMPD[11:0] with specified channel conversion result when converted data is loaded into ADC_RESULTx register.\nWhen this bit is set to 1, and CMPMATCNT is 0, the CMPF will be set once the match is hit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare Disabled
#1 : 1
Compare Enabled
End of enumeration elements list.
CMPIE : Compare Interrupt Enable\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT, CMPF bit will be asserted, in the meanwhile, if CMPIE is set to 1, a compare interrupt request is generated.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Compare function interrupt Disabled
#1 : 1
Compare function interrupt Enabled
End of enumeration elements list.
CMPCOND : Compare Condition\nNote: When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase one
#1 : 1
Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPD (ADCMPRx[27:16]), the internal match counter will increase by one
End of enumeration elements list.
CMPCH : Compare Channel Selection
bits : 3 - 7 (5 bit)
access : read-write
CMPMATCNT : Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND[2], the internal match counter will increase 1. When the internal counter reaches the value to (CMPMATCNT +1), the CMPF bit will be set.
bits : 8 - 11 (4 bit)
access : read-write
CMPD : Comparison Data\nThe 12 bits data is used to compare with conversion result of specified channel. Software can use it to monitor the external analog input pin voltage variation in scan mode without imposing a load on software.
bits : 16 - 27 (12 bit)
access : read-write
A/D Compare Register 1
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Status Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADF : A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion.\nADF is set to 1 at these two conditions:\nWhen A/D conversion ends in single mode\nWhen A/D conversion ends on all specified channels in scan mode.\nThis flag can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
CMPF0 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: When this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADC_RESULTx does not meet ADCMPR0setting
#1 : 1
Conversion result in ADC_RESULTx meets ADCMPR0setting
End of enumeration elements list.
CMPF1 : Compare Flag\nWhen the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1. And it is cleared by writing 1 to self.\nThis flag can be cleared by writing 1 to it.\nNote: when this flag is set, the matching counter will be reset to 0,and continue to count when user write 1 to clear CMPF1
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Conversion result in ADC_RESULTx does not meet ADCMPR1 setting
#1 : 1
Conversion result in ADC_RESULTx meets ADCMPR1 setting
End of enumeration elements list.
BUSY : BUSY/IDLE\nIt is read only.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
A/D converter is in idle state
#1 : 1
A/D converter is busy at conversion
End of enumeration elements list.
CHANNEL : Current Conversion Channel\nIt is read only.
bits : 4 - 8 (5 bit)
access : read-write
INITRDY : ADC Power-up Sequence Completed\nNote: This bit will be set after system reset occurred and automatically cleared by power-up event.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC has been powered up since he last system reset
#1 : 1
ADC not powered up after system reset
End of enumeration elements list.
A/D PDMA current transfer data Register
address_offset : 0x60 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AD_PDMA : ADC PDMA Current Transfer Data Register\nWhen PDMA transferring, read this register can monitor current PDMA transfer data.\nThis is a read only register.
bits : 0 - 11 (12 bit)
access : read-only
ADC Power Management Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWUPRDY : ADC Power-up Sequence Completed and Ready for Conversion
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC is not ready for conversion may be in power down state or in the progress of power up
#1 : 1
ADC is ready for conversion
End of enumeration elements list.
PWDCALEN : Power up Calibration Function Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Power up without calibration
#1 : 1
Power up with calibration
End of enumeration elements list.
PWDMOD : Power-down Mode
bits : 2 - 3 (2 bit)
access : read-write
ADC Calibration Control Register
address_offset : 0x68 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALEN : Calibraion Function Enable\nEnable this bit to turn on the calibration function block.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
(BYPASSCAL)
#1 : 1
Enabled
End of enumeration elements list.
CALSTART : Calibration Functional Blcok Start
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops calibration functional block
#1 : 1
Starts calibration functional block
End of enumeration elements list.
CALDONE : Calibrate Functional Block Complete
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not yet
#1 : 1
Selected functional block complete
End of enumeration elements list.
CALSEL : Select Calibration Functional Block
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Load calibration functional block
#1 : 1
Calibration functional block
End of enumeration elements list.
A/D calibration load word register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CALWORD : Calibration Word Register
Write to this register with the previous calibration word before load calibration action
Read this register after calibration done
Note: The calibration block contains two parts CALIBRATION and LOAD CALIBRATION if thecalibration block is config as CALIBRATION then this register represent the result of calibration when calibration is completed if config as LOAD CALIBRATION config this register before loading calibration action, after loading calibration complete, the laoded calibration word will apply to the ADC while in loading calibration function the loaded value will not be equal to the orginal CALWORD until calibration is done.
bits : 0 - 6 (7 bit)
access : read-write
ADC Channel Sampling Time Counter Register Group 0
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0SAMPCNT : Channel 0 Sampling Counter
bits : 0 - 3 (4 bit)
access : read-write
CH1SAMPCNT : Channel 1 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 4 - 7 (4 bit)
access : read-write
CH2SAMPCNT : Channel 2 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 8 - 11 (4 bit)
access : read-write
CH3SAMPCNT : Channel 3 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 12 - 15 (4 bit)
access : read-write
CH4SAMPCNT : Channel 4 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 16 - 19 (4 bit)
access : read-write
CH5SAMPCNT : Channel 5 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 20 - 23 (4 bit)
access : read-write
CH6SAMPCNT : Channel 6 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 24 - 27 (4 bit)
access : read-write
CH7SAMPCNT : Channel 7 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 28 - 31 (4 bit)
access : read-write
ADC Channel Sampling Time Counter Register Group 1
address_offset : 0x74 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8SAMPCNT : Channel 8 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 0 - 3 (4 bit)
access : read-write
CH9SAMPCNT : Channel 9 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 4 - 7 (4 bit)
access : read-write
CH10SAMPCNT : Channel 10 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 8 - 11 (4 bit)
access : read-write
CH11SAMPCNT : Channel 11 Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 12 - 15 (4 bit)
access : read-write
INTCHSAMPCNT : Internal Channel (VTEMP, AVDD, AVSS, Int_VREF, DAC0, DAC1) Sampling Counter\nThe same as Channel 0 sampling counter table.
bits : 16 - 19 (4 bit)
access : read-write
A/D Data Register 2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
A/D Data Register 3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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