\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
CRC Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCCEN : CRC Channel Enable\nSetting this bit to 1 enables CRC's operation.
bits : 0 - 0 (1 bit)
access : read-write
CRC_RST : CRC Engine Reset\nNote: When operating in CPU PIO mode, setting this bit will reload the initial seed value
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Writing 0 to this bit has no effect
#1 : 1
Writing 1 to this bit will reset the internal CRC state machine and internal buffer. The contents of control register will not be cleared. This bit will be auto cleared after few clock cycles
End of enumeration elements list.
TRIG_EN : Trigger Enable\nNote1: If this bit assert that indicates the CRC engine operation in CRC DMA mode, so don't filled any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CRC DMA data read or write transfer Enabled
End of enumeration elements list.
WDATA_RVS : Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit order reverse for CRC write data in
#1 : 1
Bit order reverse for CRC write data in (per byre)
End of enumeration elements list.
CHECKSUM_RVS : Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit order reverse for CRC checksum
#1 : 1
Bit order reverse for CRC checksum
End of enumeration elements list.
WDATA_COM : Write Data Complement
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit order reverse for CRC write data in
#1 : 1
1's complement for CRC write data in
End of enumeration elements list.
CHECKSUM_COM : Checksum Complement
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bit order reverse for CRC checksum
#1 : 1
1's complement for CRC checksum
End of enumeration elements list.
CPU_WDLEN : CPU Write Data Length
bits : 28 - 29 (2 bit)
access : read-write
CRC_MODE : CRC Polynomial Mode\n
bits : 30 - 31 (2 bit)
access : read-write
CRC Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_DMACSAR : CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only
CRC Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_DMACBCR : CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value.
bits : 0 - 15 (16 bit)
access : read-only
CRC Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABORT_IE : CRC DMA Read/Write Target Abort Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Target abort interrupt generation Disabled during CRC DMA transfer
#1 : 1
Target abort interrupt generation Enabled during CRC DMA transfer
End of enumeration elements list.
BLKD_IE : CRC DMA Transfer Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt generator Disabled during CRC DMA transfer done
#1 : 1
Interrupt generator Enabled during CRC DMA transfer done
End of enumeration elements list.
CRC Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABORT_IF : CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero\nNote: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. DMA will stop transfer and respond this event to software then go to IDLE state. When target abort occurred, software must reset DMA, and then transfer those data again
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus ERROR response received
#1 : 1
Bus ERROR response received
End of enumeration elements list.
BLKD_IF : Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not finished yet
#1 : 1
Done
End of enumeration elements list.
CRC DMA Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_DMASAR : CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote : The source address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write
CRC Write Data Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_WDATA : CRC Write Data Register
bits : 0 - 31 (32 bit)
access : read-write
CRC Seed Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_SEED : CRC Seed Register\nThis field indicates the CRC seed value.
bits : 0 - 31 (32 bit)
access : read-write
CRC Check Sum Register
address_offset : 0x88 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CRC_CHECKSUM : CRC Checksum Register\nThis field indicates the CRC checksum
bits : 0 - 31 (32 bit)
access : read-only
CRC Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC_DMABCR : CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA
bits : 0 - 15 (16 bit)
access : read-write
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