CRC_CTL (CTL)

CRC_DMACSAR (DMACSAR)

CRC_DMACBCR (DMACBCR)

CRC_DMAIER (DMAIER)

CRC_DMAISR (DMAISR)

CRC_DMASAR (DMASAR)

CRC_WDATA (WDATA)

CRC_SEED (SEED)

CRC_CHECKSUM (CHECKSUM)

CRC_DMABCR (DMABCR)

CRCCEN : CRC Channel Enable\nSetting this bit to 1 enables CRC's operation.
bits : 0 - 0 (1 bit)
access : read-write

CRC_RST : CRC Engine Reset\nNote: When operating in CPU PIO mode, setting this bit will reload the initial seed value
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TRIG_EN : Trigger Enable\nNote1: If this bit assert that indicates the CRC engine operation in CRC DMA mode, so don't filled any data in CRC_WDATA register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs, all CRC DMA transfer will be stopped. Software must reset all DMA channel, and then trigger again.
bits : 23 - 23 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDATA_RVS : Write Data Order Reverse\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHECKSUM_RVS : Checksum Reverse\nNote: If the checksum data is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WDATA_COM : Write Data Complement
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CHECKSUM_COM : Checksum Complement
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPU_WDLEN : CPU Write Data Length
bits : 28 - 29 (2 bit)
access : read-write

CRC_MODE : CRC Polynomial Mode\n
bits : 30 - 31 (2 bit)
access : read-write

CRC_DMACSAR : CRC DMA Current Source Address Register (Read Only)\nThis field indicates the source address where the CRC DMA transfer is just occurring.
bits : 0 - 31 (32 bit)
access : read-only

CRC_DMACBCR : CRC DMA Current Byte Count Register (Read Only)\nThis field indicates the current remained byte count of CRC_DMA.\nNote: CRC_RST will clear this register value.
bits : 0 - 15 (16 bit)
access : read-only

TABORT_IE : CRC DMA Read/Write Target Abort Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKD_IE : CRC DMA Transfer Done Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TABORT_IF : CRC DMA Read/Write Target Abort Interrupt Flag\nSoftware can write 1 to clear this bit to zero\nNote: The CRC_DMAISR [TABORT_IF] indicate bus master received ERROR response or not. If bus master received ERROR response, it means that target abort is happened. DMA will stop transfer and respond this event to software then go to IDLE state. When target abort occurred, software must reset DMA, and then transfer those data again
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BLKD_IF : Block Transfer Done Interrupt Flag\nThis bit indicates that CRC DMA has finished all transfer.\nSoftware can write 1 to clear this bit to zero
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CRC_DMASAR : CRC DMA Transfer Source Address Register\nThis field indicates a 32-bit source address of CRC DMA.\nNote : The source address must be word alignment
bits : 0 - 31 (32 bit)
access : read-write

CRC_WDATA : CRC Write Data Register
bits : 0 - 31 (32 bit)
access : read-write

CRC_SEED : CRC Seed Register\nThis field indicates the CRC seed value.
bits : 0 - 31 (32 bit)
access : read-write

CRC_CHECKSUM : CRC Checksum Register\nThis field indicates the CRC checksum
bits : 0 - 31 (32 bit)
access : read-only

CRC_DMABCR : CRC DMA Transfer Byte Count Register\nThis field indicates a 16-bit transfer byte count number of CRC DMA
bits : 0 - 15 (16 bit)
access : read-write