\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
External Bus Interface General Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExtEN : EBI Enable\nThis bit is the functional enable bit for EBI.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI function is disabled
#1 : 1
EBI function is enabled
End of enumeration elements list.
ExtBW16 : EBI Data Width 16-bit\nThis bit defines if the data bus is 8-bit or 16-bit.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI data width is 8-bit
#1 : 1
EBI data width is 16-bit
End of enumeration elements list.
MCLKDIV : External Output Clock Divider
bits : 8 - 10 (3 bit)
access : read-write
MCLKEN : External Clock Enable\nThis bit control if EBI generates the clock to external device.\nIf external device is a synchronous device, it's necessary to set this bit high to enable EBI generating clock to external device.\nIf the external device is an asynchronous device, keep this bit low is recommended to save power consumption.\n
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
EBI Disabled to generate clock to external device
#1 : 1
EBI Enabled to generate clock to external device
End of enumeration elements list.
ExttALE : Expand Time of ALE\nThe ALE width (tALE) to latch the address can be controlled by ExttALE.
bits : 16 - 18 (3 bit)
access : read-write
External Bus Interface Timing Control Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ExttACC : EBI Data Access Time\nExttACC define data access time (tACC).
bits : 0 - 4 (5 bit)
access : read-write
ExttAHD : EBI Data Access Hold Time\nExttAHD define data access hold time (tAHD).
bits : 8 - 10 (3 bit)
access : read-write
ExtIW2X : Idle State Cycle after Write\nWhen write action is finish, idle state is inserted and nCS return to high if ExtIW2X is not zero.
bits : 12 - 15 (4 bit)
access : read-write
ExtIR2W : Idle State Cycle between Read-Write\nWhen read action is finish and next action is going to write, idle state is inserted and nCS return to high if ExtIR2W is not zero.
bits : 16 - 19 (4 bit)
access : read-write
ExtIR2R : Idle State Cycle between Read-Read\nWhen read action is finish and next action is going to read, idle state is inserted and nCS return to high if ExtIR2R is not zero.
bits : 24 - 27 (4 bit)
access : read-write
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