\n
address_offset : 0x0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x180 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x40 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC0 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x140 Bytes (0x0)
size : 0x28 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x200 Bytes (0x0)
size : 0x158 byte (0x0)
mem_usage : registers
protection : not protected
GPIO Port A Pin I/O Mode Control Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMD0 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD1 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD2 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD3 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD4 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD5 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD6 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD7 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD8 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD9 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD10 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD11 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD12 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD13 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD14 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
PMD15 : GPIO Port [x] Pin [n] Mode Control\nDetermine the I/O type of GPIO port [x] pin [n]\nNote: For GPIOF_PMD, PMD6 ~ PMD15 are reserved.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
GPIO port [x] pin [n] is in INPUT mode
#01 : 1
GPIO port [x] pin [n] is in OUTPUT mode
#10 : 2
GPIO port [x] pin [n] is in Open-Drain mode
#11 : 3
Reserved
End of enumeration elements list.
GPIO Port A Pin Value Register
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PIN0 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-only
PIN1 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-only
PIN2 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-only
PIN3 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-only
PIN4 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-only
PIN5 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-only
PIN6 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-only
PIN7 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-only
PIN8 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-only
PIN9 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-only
PIN10 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-only
PIN11 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-only
PIN12 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-only
PIN13 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-only
PIN14 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-only
PIN15 : GPIO Port [x] Pin [n] Value\nThe value read from each of these bit reflects the actual status of the respective GPI/O pin\nNote: For GPIOF_PIN, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-only
GPIO Port E Pin I/O Mode Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Pin OFF Digital Enable Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Data Output Value Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Data Output Write Mask Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Pin Value Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E De-bounce Enable Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Interrupt Mode Control Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Interrupt Enable Register
address_offset : 0x11C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Interrupt Trigger Source Status Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Pull-Up Enable Register
address_offset : 0x124 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A De-bounce Enable Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBEN0 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN1 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN2 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN3 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN4 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN5 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN6 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN7 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN8 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN9 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN10 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN11 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN12 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN13 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN14 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
DBEN15 : GPIO Port [x] Pin [n] Input Signal De-bounce Enable
DBEN[n] used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal transition is seen as the signal bounce and will not trigger the interrupt.
DBEN[n] is used for edge-trigger interrupt only, and ignored for level trigger interrupt
The de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note: For GPIOF_DBEN, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The GPIO port [x] Pin [n] input signal de-bounce function is disabled
#1 : 1
The GPIO port [x] Pin [n] input signal de-bounce function is enabled
End of enumeration elements list.
GPIO Port F Pin I/O Mode Control Register
address_offset : 0x140 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Pin OFF Digital Enable Register
address_offset : 0x144 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Data Output Value Register
address_offset : 0x148 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Data Output Write Mask Register
address_offset : 0x14C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Pin Value Register
address_offset : 0x150 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F De-bounce Enable Register
address_offset : 0x154 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Interrupt Mode Control Register
address_offset : 0x158 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Interrupt Enable Register
address_offset : 0x15C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Interrupt Trigger Source Status Register
address_offset : 0x160 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Pull-Up Enable Register
address_offset : 0x164 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Interrupt Mode Control Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMD0 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD1 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD2 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD3 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD4 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD5 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD6 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD7 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD8 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD9 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD10 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD11 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD12 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD13 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD14 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
IMD15 : GPIO Port [x] Pin [n] Edge or Level Detection Interrupt Control\nIMD[n] used to control the interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger, the trigger source is control de-bounce. If the interrupt is by level trigger, the input source is sampled by one clock and the generate the interrupt \nIf set pin as the level trigger interrupt, then only one level can be set on the registers GPIOX_IER. If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur\nThe de-bounce function is valid for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.\nNote: For GPIOF_IMD, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
Edge trigger interrupt
#1 : 1
Level trigger interrupt
End of enumeration elements list.
De-bounce Cycle Control Register
address_offset : 0x180 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUEN : De-bounce Sampling Cycle Selection
bits : 0 - 0 (1 bit)
access : read-write
DBCLKSRC : De-bounce Counter Clock Source Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce counter Clock Source is the HCLK
#1 : 1
De-bounce counter Clock Source is the internal 10 kHz clock
End of enumeration elements list.
DBCLK_ON : De-bounce Clock Enable\nThis bit controls if the de-bounce clock is enabled.\nHowever, if GPI/O pin's interrupt is enabled, the de-bounce clock will be enabled automatically no matter what the DBCLK_ON value is.\nIf CPU is in sleep mode, this bit didn't take effect. And only the GPI/O pin with interrupt enable could get de-bounce clock.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
De-bounce clock Disabled
#1 : 1
De-bounce clock Enabled
End of enumeration elements list.
GPIO Port A Interrupt Enable Register
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FIER0 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER1 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER2 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER3 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER4 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER5 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER6 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER7 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER8 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER9 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER10 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER11 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER12 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER13 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER14 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
FIER15 : GPIO Port [x] Pin [n] Interrupt Enable by Input Falling Edge or Input Level Low
FIER[n] used to enable the interrupt for each of the corresponding input GPIO_PIN[n]. Set bit 1 also enable the pin wake-up function
When set the FIER[n] bit 1 :
If the interrupt is level mode trigger, the input PIN[n] state at level low will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[n] state change from high-to-low will generate the interrupt.
Note: For GPIOF_IER, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[n] state low-level or high-to-low change interrupt Disabled
#1 : 1
PIN[n] state low-level or high-to-low change interrupt Enabled
End of enumeration elements list.
RIER0 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER1 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER2 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER3 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER4 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER5 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER6 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER7 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER8 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER9 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER10 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER11 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER12 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER13 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER14 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
RIER15 : GPIO Port [x] Pin [n] Interrupt Enable by Input Rising Edge or Input Level High
RIER[x] used to enable the interrupt for each of the corresponding input GPIO_PIN[x]. Set bit 1 also enable the pin wake-up function
When set the RIER[x] bit 1 :
If the interrupt is level mode trigger, the input PIN[x] state at level high will generate the interrupt.
If the interrupt is edge mode trigger, the input PIN[x] state change from low-to-high will generate the interrupt.
Note: For GPIOF_IE, bits [31:22] are reserved.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
PIN[x] level-high or low-to-high interrupt Disabled
#1 : 1
PIN[x] level-high or low-to-high interrupt Enabled
End of enumeration elements list.
GPIO Port A Interrupt Trigger Source Status Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISRC0 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC1 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC2 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC3 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC4 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC5 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC6 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC7 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC8 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC9 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC10 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC11 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC12 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC13 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC14 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
ISRC15 : GPIO Port [x] Pin [n] Interrupt Trigger Source Indicator\nRead :\nNote: For GPIOF_ISRC, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
No interrupt at Port x[n]\nNo action
#1 : 1
Port x[n] generate an interrupt\nClear the correspond pending interrupt
End of enumeration elements list.
GPIO Port A Bit 0 Data Register
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO : GPIO Port [x] Pin [n] I/O Data\nThis field supports the bit operation mode on related GPIO port [x] pin [n].\nWriting this filed to set the corresponding GPIO port [x] pin [n] output value while reading this field to get the corresponding GPIO port [x] pin [n] value.\nRead:\n\nNote: The write operation will not be affected by register GPIOx_DMASK.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO port [x] pin [n] value is low.\nSet corresponding GPIO port [x] pin [n] to low
#1 : 1
The corresponding GPIO port [x] pin [n] value is high.\nSet corresponding GPIO port [x] pin [n] to high
End of enumeration elements list.
GPIO Port A Bit 1 Data Register
address_offset : 0x204 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 2 Data Register
address_offset : 0x208 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 3 Data Register
address_offset : 0x20C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 4 Data Register
address_offset : 0x210 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 5 Data Register
address_offset : 0x214 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 6 Data Register
address_offset : 0x218 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 7 Data Register
address_offset : 0x21C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 8 Data Register
address_offset : 0x220 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 9 Data Register
address_offset : 0x224 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 10 Data Register
address_offset : 0x228 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 11 Data Register
address_offset : 0x22C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 12 Data Register
address_offset : 0x230 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 13 Data Register
address_offset : 0x234 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 14 Data Register
address_offset : 0x238 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 15 Data Register
address_offset : 0x23C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Pull-Up Enable Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PUEN0 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN1 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN2 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN3 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN4 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN5 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN6 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN7 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN8 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN9 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN10 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN11 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN12 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN13 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN14 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
PUEN15 : GPIO Port [x] Pin [n] Pull-Up Enable Register\nRead :\n\nNote: For GPIOF_PUEN, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Disabled
#1 : 1
GPIO port [A/B/C/D/E/F] bit [n] pull-up resistor Enabled
End of enumeration elements list.
GPIO Port B Bit 0 Data Register
address_offset : 0x240 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 1 Data Register
address_offset : 0x244 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 2 Data Register
address_offset : 0x248 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 3 Data Register
address_offset : 0x24C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 4 Data Register
address_offset : 0x250 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 5 Data Register
address_offset : 0x254 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 6 Data Register
address_offset : 0x258 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 7 Data Register
address_offset : 0x25C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 8 Data Register
address_offset : 0x260 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 9 Data Register
address_offset : 0x264 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 10 Data Register
address_offset : 0x268 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 11 Data Register
address_offset : 0x26C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 12 Data Register
address_offset : 0x270 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 13 Data Register
address_offset : 0x274 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 14 Data Register
address_offset : 0x278 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Bit 15 Data Register
address_offset : 0x27C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 0 Data Register
address_offset : 0x280 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 1 Data Register
address_offset : 0x284 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 2 Data Register
address_offset : 0x288 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 3 Data Register
address_offset : 0x28C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 4 Data Register
address_offset : 0x290 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 5 Data Register
address_offset : 0x294 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 6 Data Register
address_offset : 0x298 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 7 Data Register
address_offset : 0x29C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 8 Data Register
address_offset : 0x2A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 9 Data Register
address_offset : 0x2A4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 10 Data Register
address_offset : 0x2A8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 11 Data Register
address_offset : 0x2AC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 12 Data Register
address_offset : 0x2B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 13 Data Register
address_offset : 0x2B4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 14 Data Register
address_offset : 0x2B8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Bit 15 Data Register
address_offset : 0x2BC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 0 Data Register
address_offset : 0x2C0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 1 Data Register
address_offset : 0x2C4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 2 Data Register
address_offset : 0x2C8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 3 Data Register
address_offset : 0x2CC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 4 Data Register
address_offset : 0x2D0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 5 Data Register
address_offset : 0x2D4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 6 Data Register
address_offset : 0x2D8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 7 Data Register
address_offset : 0x2DC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 8 Data Register
address_offset : 0x2E0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 9 Data Register
address_offset : 0x2E4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 10 Data Register
address_offset : 0x2E8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 11 Data Register
address_offset : 0x2EC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 12 Data Register
address_offset : 0x2F0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 13 Data Register
address_offset : 0x2F4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 14 Data Register
address_offset : 0x2F8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Bit 15 Data Register
address_offset : 0x2FC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 0 Data Register
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 1 Data Register
address_offset : 0x304 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 2 Data Register
address_offset : 0x308 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 3 Data Register
address_offset : 0x30C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 4 Data Register
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 5 Data Register
address_offset : 0x314 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 6 Data Register
address_offset : 0x318 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 7 Data Register
address_offset : 0x31C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 8 Data Register
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 9 Data Register
address_offset : 0x324 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 10 Data Register
address_offset : 0x328 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 11 Data Register
address_offset : 0x32C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 12 Data Register
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 13 Data Register
address_offset : 0x334 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 14 Data Register
address_offset : 0x338 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port E Bit 15 Data Register
address_offset : 0x33C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Bit 0 Data Register
address_offset : 0x340 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Bit 1 Data Register
address_offset : 0x344 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Bit 2 Data Register
address_offset : 0x348 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Bit 3 Data Register
address_offset : 0x34C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Bit 4 Data Register
address_offset : 0x350 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port F Bit 5 Data Register
address_offset : 0x354 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Pin OFF Digital Enable Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFD0 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD1 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD2 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD3 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD4 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD5 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD6 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD7 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD8 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD9 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD10 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD11 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD12 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD13 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD14 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
OFFD15 : GPIO Port [x] Pin [n] Digital Input Path Disable\nDetermine if the digital input path of GPIO port [x] pin [n] is disabled.\nNote: For GPIOF_OFFD, bits [31:22] are reserved.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Digital input path of GPIO port [x] pin [n] Enabled
#1 : 1
Digital input path of GPIO port [x] pin [n] Disabled (tied digital input to low)
End of enumeration elements list.
GPIO Port B Pin I/O Mode Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Pin OFF Digital Enable Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Data Output Value Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Data Output Write Mask Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Pin Value Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B De-bounce Enable Register
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Interrupt Mode Control Register
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Interrupt Enable Register
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Interrupt Trigger Source Status Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port B Pull-Up Enable Register
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Data Output Value Register
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DOUT0 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT1 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT2 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT3 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT4 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT5 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT6 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT7 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT8 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT9 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT10 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT11 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT12 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT13 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT14 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
DOUT15 : GPIO Port [x] Pin [n] Output Value\nEach of these bits controls the status of a GPIO port [x] pin [n] when the GPI/O pin is configures as output or open-drain mode\nNote: For GPIOF_DOUT, bits [15:6] are reserved.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO port [x] Pin [n] will drive Low if the corresponding output mode enabling bit is set
#1 : 1
GPIO port [x] Pin [n] will drive High if the corresponding output mode enabling bit is set
End of enumeration elements list.
GPIO Port C Pin I/O Mode Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Pin OFF Digital Enable Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Data Output Value Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Data Output Write Mask Register
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Pin Value Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C De-bounce Enable Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Interrupt Mode Control Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Interrupt Enable Register
address_offset : 0x9C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Interrupt Trigger Source Status Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port C Pull-Up Enable Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port A Data Output Write Mask Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMASK0 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK1 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK2 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK3 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK4 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK5 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK6 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK7 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK8 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK9 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK10 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK11 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK12 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK13 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK14 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
DMASK15 : GPIO Port [x] Pin [n] Data Output Write Mask
These bits are used to protect the corresponding register of GPIOx_DOUT bit [n]. When set the DMASK[n] to 1 , the corresponding DOUT[n] bit is protected. The write signal is masked, write data to the protect bit is ignored
Note: For GPIOF_DMASK, bits [15:6] are reserved.
Note: These mask bits only take effect while CPU is doing write operation to register GPIOx_DOUT. If CPU is doing write operation to register GPIO[x][n], these mask bits will not take effect.
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
The corresponding GPIO_DOUT bit [n] can be updated
#1 : 1
The corresponding GPIO_DOUT bit [n] is protected
End of enumeration elements list.
GPIO Port D Pin I/O Mode Control Register
address_offset : 0xC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Pin OFF Digital Enable Register
address_offset : 0xC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Data Output Value Register
address_offset : 0xC8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Data Output Write Mask Register
address_offset : 0xCC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Pin Value Register
address_offset : 0xD0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D De-bounce Enable Register
address_offset : 0xD4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Interrupt Mode Control Register
address_offset : 0xD8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Interrupt Enable Register
address_offset : 0xDC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Interrupt Trigger Source Status Register
address_offset : 0xE0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIO Port D Pull-Up Enable Register
address_offset : 0xE4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
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