\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x28 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x58 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x60 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x90 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x30 Bytes (0x0)
size : 0x24 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x7C Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xA0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
Part Device Identification Number Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PDID : Part Device Identification Number (Read Only)\nThis register reflects device part number code. Software can read this register to identify which device is used.
bits : 0 - 31 (32 bit)
access : read-only
Register Lock Control Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGLCTL : Register Lock Control Code (Write Only)
Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value 59h , 16h , 88h to this field. After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Register Lock Control Disable Index (Read Only)
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : 0
Write-protection Enabled for writing protected registers. Any write to the protected register is ignored
1 : 1
Write-protection Disabled for writing protected registers
End of enumeration elements list.
Reset Pin Debounce Clock Selection Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTPDBCLK : Reset Pin Debounce Clock Selection Bit\nBefore swtch clock, both clock sources must be enabled.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC2 is slected as reset pin debounce clock
#1 : 1
HIRC0 is slected as reset pin debounce clock.(.default)
End of enumeration elements list.
Temperature Sensor Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTEMPEN : Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Temperature sensor function Disabled (default)
#1 : 1
Temperature sensor function Enabled
End of enumeration elements list.
RC Clock Filter Control Register
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIRC0FEN : HIRC0 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC0clock filter function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC0clock filter function Disabled
#1 : 1
HIRC0clock filter function Enabled (default)
End of enumeration elements list.
HIRC1FEN : HIRC1 Clock Filter Enable Bit\nThis bit is used to enable/disable HIRC1clock filter function.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
HIRC1clock filter function Disabled
#1 : 1
HIRC1clock filter function Enabled (default)
End of enumeration elements list.
MRCFEN : MRC Clock Filter Enable Bit\nThis bit is used to enable/disable MRC clock filter function.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
4MHz MRC clock filter function Disabled
#1 : 1
4MHz MRC clock filter function Enabled (default)
End of enumeration elements list.
GPIOA Low Byte Multiple Function Control Register
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA0MFP : PA.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[0]
#0001 : 1
ADC analog input0
#0010 : 2
Comparator1 P-end input
#0011 : 3
Timer0 capture input
#0101 : 5
PWM0 channel2 output/capture input
End of enumeration elements list.
PA1MFP : PA.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[1]
#0001 : 1
ADC analog input1
#0010 : 2
Comparator1 N-end input
#0110 : 6
SPI0 2ndMISO (Master In, Slave Out) pin
End of enumeration elements list.
PA2MFP : PA.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[2]
#0001 : 1
ADC analog input2
#0101 : 5
Data receiver input pin for UART1
End of enumeration elements list.
PA3MFP : PA.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[3]
#0001 : 1
ADC analog input3
#0101 : 5
Data transmitter output pin for UART1
#0110 : 6
SPI31stMOSI (Master Out, Slave In) pin
End of enumeration elements list.
PA4MFP : PA.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[4]
#0001 : 1
ADC analog input4
#0101 : 5
I2C0 data input/output pin
#0110 : 6
SPI31stMISO (Master In, Slave Out) pin
End of enumeration elements list.
PA5MFP : PA.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[5]
#0001 : 1
ADC analog input5
#0101 : 5
I2C0 clock pin
#0110 : 6
SPI3 serial clock pin
End of enumeration elements list.
PA6MFP : PA.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[6]
#0001 : 1
ADC analog input6
#0010 : 2
Comparator1 output
#0011 : 3
Timer3 capture input
#0100 : 4
Timer3 external counter input
#0101 : 5
PWM0 channel3 output/capture input
#0111 : 7
Timer3 toggle output
End of enumeration elements list.
GPIOA High Byte Multiple Function Control Register
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA8MFP : PA.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[8]
#0001 : 1
I2C0 data input/output pin
#0010 : 2
Timer0 external counter input
#0011 : 3
SmartCard0 clock pin
#0100 : 4
SPI2 slave select pin
#0101 : 5
Timer0 toggle output
#0110 : 6
UART0 Clear to Send input pin
End of enumeration elements list.
PA9MFP : PA.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[9]
#0001 : 1
I2C0 clock pin
#0010 : 2
Timer1 external counter input
#0011 : 3
SmartCard0 data pin
#0100 : 4
SPI0 serial clock pin
#0101 : 5
Timer1 toggle output
#0110 : 6
UART1 Request to Send output pin
#0111 : 7
Snooper pin
End of enumeration elements list.
PA10MFP : PA.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[10]
#0001 : 1
I2C1 data input/output pin
#0010 : 2
Timer2 external counter input
#0011 : 3
SmartCard0 power pin
#0100 : 4
SPI21stMISO (Master In, Slave Out) pin
#0101 : 5
Timer2 toggle output
End of enumeration elements list.
PA11MFP : PA.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[11]
#0001 : 1
I2C1 clock pin
#0010 : 2
Timer3 external counter input
#0011 : 3
SmartCard0 reset pin
#0100 : 4
SPI21stMOSI (Master Out, Slave In) pin
#0101 : 5
Timer3 toggle output
End of enumeration elements list.
PA12MFP : PA.12 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[12]
#0001 : 1
PWM0 channel0 output/capture input
#0011 : 3
Timer0 capture input
#0101 : 5
I2C0 data input/output pin
End of enumeration elements list.
PA13MFP : PA.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[13]
#0001 : 1
PWM0 channel1 output/capture input
#0011 : 3
Timer1 capture input
#0101 : 5
I2C0 clock pin
End of enumeration elements list.
PA14MFP : PA.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[14]
#0001 : 1
PWM0 channel2 output/capture input
#0010 : 2
I2C1 data input/output pin
#0011 : 3
I2C1 data input/output pin
#0101 : 5
Timer2 external counter input
#0110 : 6
Data receiver input pin for UART0
#0111 : 7
Timer2 toggle output
End of enumeration elements list.
PA15MFP : PA.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOA[15]
#0001 : 1
PWM0 channel3 output/capture input
#0010 : 2
I2C1 clock pin
#0011 : 3
Timer1 capture input
#0100 : 4
SmartCard0 power pin
#0110 : 6
Data transmitter output pin for UART0
#0111 : 7
Timer3 toggle output
End of enumeration elements list.
GPIOB Low Byte Multiple Function Control Register
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB0MFP : PB.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[0]
#0001 : 1
Data receiver input pin for UART0
#0011 : 3
SPI11stMOSI (Master Out, Slave In) pin
End of enumeration elements list.
PB1MFP : PB.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[1]
#0001 : 1
Data transmitter output pin for UART0
#0011 : 3
SPI11stMISO (Master In, Slave Out) pin
End of enumeration elements list.
PB2MFP : PB.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[2]
#0001 : 1
UART0 Request to Send output pin
#0011 : 3
SPI1 serial clock pin
#0100 : 4
Frequency Divider output pin
End of enumeration elements list.
PB3MFP : PB.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[3]
#0001 : 1
UART0 Clear to Send input pin
#0011 : 3
SPI1 slave select pin
#0100 : 4
SmartCard1 card detect pin
End of enumeration elements list.
PB4MFP : PB.4 Multi-function Pin Selection
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[4]
#0001 : 1
Data receiver input pin for UART1
#0011 : 3
SmartCard0 card detect pin
#0100 : 4
SPI2 slave select pin
#0110 : 6
RTC 1Hz output
End of enumeration elements list.
PB5MFP : PB.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[5]
#0001 : 1
Data transmitter output pin for UART1
#0011 : 3
SmartCard0 reset pin
#0100 : 4
SPI2 serial clock pin
End of enumeration elements list.
PB6MFP : PB.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[6]
#0001 : 1
UART1 Request to Send output pin
#0100 : 4
SPI21stMISO (Master In, Slave Out) pin
End of enumeration elements list.
PB7MFP : PB.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[7]
#0001 : 1
UART1 Clear to Send input pin
End of enumeration elements list.
GPIOB High Byte Multiple Function Control Register
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PB8MFP : PB.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[8]
#0001 : 1
ADC external trigger input
#0010 : 2
Timer0 external counter input
#0011 : 3
External interrupt0 input pin
#0100 : 4
Timer0 toggle output
#0111 : 7
Snooper pin
End of enumeration elements list.
PB9MFP : PB.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[9]
#0001 : 1
SPI1 slave select pin
#0010 : 2
Timer2 external counter input
#0100 : 4
Timer2 toggle output
#0101 : 5
External interrupt0 input pin
End of enumeration elements list.
PB10MFP : PB.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[10]
#0001 : 1
SPI0 1stMOSI (Master Out, Slave In) pin
#0100 : 4
Timer2 toggle output
#0101 : 5
SPI0 slave select pin
End of enumeration elements list.
PB11MFP : PB.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[11]
#0001 : 1
PWM0 channel4 output/capture input
#0010 : 2
Timer3 external counter input
#0100 : 4
Timer3 toggle output
#0101 : 5
SPI0 1stMISO (Master In, Slave Out) pin
End of enumeration elements list.
PB13MFP : PB.13 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[13]
#0011 : 3
SPI22ndMISO (Master In, Slave Out) pin
#0111 : 7
Snooper pin
End of enumeration elements list.
PB14MFP : PB.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[14]
#0001 : 1
External interrupt0 input pin
#0011 : 3
SPI22ndMOSI (Master Out, Slave In) pin
#0100 : 4
SPI2 slave select pin
End of enumeration elements list.
PB15MFP : PB.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOB[15]
#0001 : 1
External interrupt1 input pin
#0011 : 3
Snooper pin
#0100 : 4
SmartCard1 card detect pin
End of enumeration elements list.
System Reset Status Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PORF : POR Reset Flag
The POR reset flag is set by the Reset Signal from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from POR or CHIPRST
#1 : 1
Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system
End of enumeration elements list.
PINRF : NRESET Pin Reset Flag
The nRESET pin reset flag is set by the Reset Signal from the nRESET Pin to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from nRESET pin
#1 : 1
Pin nRESET had issued the reset signal to reset the system
End of enumeration elements list.
WDTRF : WDT Reset Flag
The WDT reset flag is set by the Reset Signal from the Watchdog Timer to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from watchdog timer or window watchdog timer
#1 : 1
The watchdog timer had issued the reset signal to reset the system
End of enumeration elements list.
LVRF : LVR Reset Flag
The LVR reset flag is set by the Reset Signal from the Low-VoltageReset controller to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from LVR
#1 : 1
The LVR had issued the reset signal to reset the system
End of enumeration elements list.
BODRF : BOD Reset Flag
The BOD reset flag is set by the Reset Signal from the Brown-Out Detector to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from BOD
#1 : 1
The BOD had issued the reset signal to reset the system
End of enumeration elements list.
SYSRF : System Reset Flag
The system reset flag is set by the Reset Signal from the Cortex-M0 Core to indicate the previous reset source.
Note: Write 1 to clear this bit to 0.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M0
#1 : 1
The Cortex-M0 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M0 core
End of enumeration elements list.
CPURF : CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M0 Core and Flash Memory Controller (FMC).\nNote: Write 1 to clear this bit to 0.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from CPU
#1 : 1
The Cortex-M0 Core and FMC are reset by software setting CPURST to 1
End of enumeration elements list.
LOCKRF : Lockup Reset Flag
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
No reset from Cortex-M0
#1 : 1
The Cortex-M0 had issued the reset signal to reset the system by Cortex-M0 lockup event
End of enumeration elements list.
GPIOC Low Byte Multiple Function Control Register
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC0MFP : PC.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[0]
#0001 : 1
SPI0 slave select pin
#0100 : 4
SmartCard1 clock pin
#0101 : 5
PWM0 break1 input 1
End of enumeration elements list.
PC1MFP : PC.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[1]
#0001 : 1
SPI0 serial clock pin
#0100 : 4
SmartCard1 data pin
#0101 : 5
PWM0 break1 input 0
End of enumeration elements list.
PC2MFP : PC.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[2]
#0001 : 1
SPI0 1st MISO (Master In, Slave Out) pin
#0100 : 4
SmartCard1 power pin
#0101 : 5
PWM0 break0 input 1
End of enumeration elements list.
PC3MFP : PC.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[3]
#0001 : 1
SPI0 1stMOSI (Master Out, Slave In) pin
#0100 : 4
SmartCard1 reset pin
#0101 : 5
PWM0 break0 input 0
End of enumeration elements list.
PC6MFP : PC.6 Pin Fuction Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[6]
#0001 : 1
Data receiver input pin for UART1
#0011 : 3
Timer0 capture input
#0100 : 4
SmartCard1 card detect pin
#0101 : 5
PWM0 channel0 output/capture input
End of enumeration elements list.
PC7MFP : PC.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[7]
#0001 : 1
Data transmitter output pin for UART1
#0010 : 2
ADC analog input7
#0011 : 3
Timer1 capture input
#0101 : 5
PWM0 channel1 output/capture input
End of enumeration elements list.
GPIOC High Byte Multiple Function Control Register
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC8MFP : PC.8 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[8]
#0001 : 1
SPI1 slave select pin
#0101 : 5
I2C1 data input/output pin
End of enumeration elements list.
PC9MFP : PC.9 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[9]
#0001 : 1
SPI1 serial clock pin
#0101 : 5
I2C1 clock pin
End of enumeration elements list.
PC10MFP : PC.10 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[10]
#0001 : 1
SPI0 1stMISO (Master In, Slave Out) pin
#0101 : 5
Data receiver input pin for UART1
End of enumeration elements list.
PC11MFP : PC.11 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[11]
#0001 : 1
SPI1 1stMOSI (Master Out, Slave In) pin
#0101 : 5
Data transmitter output pin for UART1
End of enumeration elements list.
PC14MFP : PC.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[14]
#0001 : 1
UART0 Clear to Send input pin
End of enumeration elements list.
PC15MFP : PC.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOC[15]
#0001 : 1
UART1 Request to Send output pin
#0011 : 3
Timer0 capture input
End of enumeration elements list.
GPIOD Low Byte Multiple Function Control Register
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD6MFP : PD.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOD[6]
#0011 : 3
SPI12ndMOSI (Master Out, Slave In) pin
#0100 : 4
SmartCard1 reset pin
End of enumeration elements list.
PD7MFP : PD.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOD[7]
#0011 : 3
SPI12ndMISO (Master In, Slave Out) pin
#0100 : 4
SmartCard1 power pin
End of enumeration elements list.
GPIOD High Byte Multiple Function Control Register
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PD14MFP : PD.14 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOD[14]
#0001 : 1
SPI0 2ndMOSI (Master Out, Slave In) pin
End of enumeration elements list.
PD15MFP : PD.15 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOD[15]
#0001 : 1
SPI0 2ndMISO (Master In, Slave Out) pin
#0100 : 100
SmartCard1 clock pin
End of enumeration elements list.
GPIOE Low Byte Multiple Function Control Register
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE5MFP : PE.5 Multi-function Pin Selection
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOE[5]
#0001 : 1
PWM0 channel5 output/capture input
#0110 : 6
RTC 1Hz output
End of enumeration elements list.
GPIOF Low Byte Multiple Function Control Register
address_offset : 0x58 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PF0MFP : PF.0 Multi-function Pin Selection
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOF[1].\nSerial wired debugger data pin
#0101 : 5
External interrupt0 input pin
End of enumeration elements list.
PF1MFP : PF.1 Multi-function Pin Selection
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOF[1].\nSerial wired debugger clock pin
#0100 : 4
Frequency Divider output pin
#0101 : 5
External interrupt1 input pin
End of enumeration elements list.
PF2MFP : PF.2 Multi-function Pin Selection
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOF[2].\nExternal 4~36 MHz (high speed) crystal output pin
End of enumeration elements list.
PF3MFP : PF.3 Multi-function Pin Selection
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOF[3].\nExternal 4~36 MHz (high speed) crystal input pin
End of enumeration elements list.
PF6MFP : PF.6 Multi-function Pin Selection
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOF[6].\nExternal 32.768 kHz crystal output pin(default)
#0001 : 1
I2C1 data input/output pin
End of enumeration elements list.
PF7MFP : PF.7 Multi-function Pin Selection
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
#0000 : 0
GPIOF[7].\nExternal 32.768 kHz crystal input pin(default)
#0001 : 1
I2C1 clock pin
#0011 : 3
SmartCard0 card detect pin
End of enumeration elements list.
Power-on-Reset Controller Register
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POROFF : Power-on Reset Enable Bit (Write Protect)\nWhen powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.\nThe POR function will be active again when this field is set to another value or chip is reset by other reset source, including:\nnRESET, Watchdog, BOD reset, ICE reset command and the software-chip reset function.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 15 (16 bit)
access : read-write
Brown-out Detector Controller Register
address_offset : 0x64 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BODEN : Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBODEN (CONFIG0 []).This Brown-out Detecto only valid in Normal Mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector function Disabled in Normal mode
#1 : 1
Brown-out Detector function Enabled in Normal mode
End of enumeration elements list.
BODIE : BOD Interrupt Enable Control(Write Protect)\nNote1: While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt does not issue when BOD occurs in Normal Mode
#1 : 1
Interrupt issues when BOD occursi in Normal Mode
End of enumeration elements list.
BODREN : Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by flash controller user configuration register CBOV(CONFIG0[]) bit.\nNote1: While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out RESET function Disabled in Normal Mode
#1 : 1
Brown-out RESET function Enabled in Normal Mode
End of enumeration elements list.
BODIF : Brown-out DetectorInterrupt Flag\nNote: Write 1 to clear this bit to 0.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector does not detect any voltage drift at VDD down through or up through the target detected voltage after interrupt is enabled
#1 : 1
When Brown-out Detectordetects the VDD is dropped down through the target detected voltage or the VDD is raised up through the target detected voltage, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled
End of enumeration elements list.
BODOUT : Brown-out DetectorOutuput Status\nIt means the detected voltage is lower than BODVL setting. If the BODEN is 0, BOD function disabled , this bit always responds 0.\nNote: This bit is ready-only.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Brown-out Detector output status is 0
#1 : 1
Brown-out Detector output status is 1
End of enumeration elements list.
LVREN : Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.\nNote1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote3: LIRC must be enabled before enable LVR.
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Voltage Reset function Disabled
#1 : 1
Low Voltage Reset function Enabled
End of enumeration elements list.
LPBODEN : Low Power Brown-out Detector Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.\nNote2: LIRC must be enabled before enable BOD.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Power Brown-out Detector function Disabled in Power-down mode
#1 : 1
Low Power Brown-out Detector function Enabled in Power-down mode
End of enumeration elements list.
LPBODVL : Low Power Brown-out Detector Threshold Voltage Selection(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low Power Brown-Out Detector threshold voltageis 2.0V in Power-down mode
#1 : 1
Low Power Brown-Out Detector threshold voltageis 2.5V in Power-down mode
End of enumeration elements list.
LPBODIE : Low Power BOD Interrupt Enable Control(Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the LPBOD function is enabled (LPBODEN high) and LPBOD interrupt function is enabled (LPBODIEhigh), LPBOD will assert an interrupt if BODOUT is high. Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt does not issue when LPBOD occurs in Power-down mode
#1 : 1
Interrupt issues when LPBOD occurs in Power-down mode
End of enumeration elements list.
LPBODREN : Low Power Brown-out Reset Enable Bit (Write Protect)\nLow Power Brown-out Dector only valid in Power-down mode.\nNote1: While the Low power Brown-out Detector function is enabled (LPBODEN high) and LPBOD reset function is enabled (LPBODREN high), LPBOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).\nNote2: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low power Brown-out dector RESET function Disabled in Power-down mode
#1 : 1
Low Power Brown-out dector RESET function Enabled in Power-down mode
End of enumeration elements list.
BODVL : Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by flash controller user configuration register CBOV (CONFIG0[]).\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 12 - 15 (4 bit)
access : read-write
Enumeration:
#0000 : 0
Brown-Out Detector threshold voltageis 1.7V
#0001 : 1
Brown-Out Detector threshold voltageis 1.8V
#0010 : 2
Brown-Out Detector threshold voltageis 1.9V
#0011 : 3
Brown-Out Detector threshold voltageis 2.0V
#0100 : 4
Brown-Out Detector threshold voltageis 2.1V
#0101 : 5
Brown-Out Detector threshold voltageis 2.2V
#0110 : 6
Brown-Out Detector threshold voltageis 2.3V
#0111 : 7
Brown-Out Detector threshold voltageis 2.4V
#1000 : 8
Brown-Out Detector threshold voltageis 2.5V
#1001 : 9
Brown-Out Detector threshold voltageis 2.6V
#1010 : 10
Brown-Out Detector threshold voltageis 2.7V
#1011 : 11
Brown-Out Detector threshold voltageis 2.8V
#1100 : 12
Brown-Out Detector threshold voltageis 2.9V
#1101 : 13
Brown-Out Detector threshold voltageis 3.0V
#1110 : 14
Brown-Out Detector threshold voltageis 3.1V
#1111 : 15
Reserved
End of enumeration elements list.
LPBOD20TRIM : Low Power BOD 2.0 TRIM Value(Write Protect)
This value is used to control BOD20 detect voltage level in power-down mode, nominal 2.0 V. Higher trim value, higher detection voltage.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 16 - 19 (4 bit)
access : read-write
LPBOD25TRIM : Low Power BOD 2.5 TRIM Value(Write Protect)
This value is used to control LPBOD25 detect voltage level in power-down mode, nominal 2.5 V. Higher trim value, higher detection voltage.
Note: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 20 - 23 (4 bit)
access : read-write
BODDGSEL : Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#000 : 0
BOD output is sampled by RC10K clock
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
LVRDGSEL : LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected. Refer to the SYS_REGLCTL register.
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#000 : 0
Without de-glitch function
#001 : 1
4 system clock (HCLK)
#010 : 2
8 system clock (HCLK)
#011 : 3
16 system clock (HCLK)
#100 : 4
32 system clock (HCLK)
#101 : 5
64 system clock (HCLK)
#110 : 6
128 system clock (HCLK)
#111 : 7
256 system clock (HCLK)
End of enumeration elements list.
Brown-out Detector Status Register
address_offset : 0x68 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Internal Voltage Reference Control Register
address_offset : 0x6C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BGPEN : Band-gap Enable Control(Write Protect)\nBand-gap is the reference voltage of internal reference voltage. User must enable band-gap if want to enable internal 1.5, 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Band-gap Disabled
#1 : 1
Band-gap Enabled
End of enumeration elements list.
REGEN : Regulator Enable Control(Write Protect)\nEnable internal 1.5, 1.8V or 2.5V reference voltage.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Regulator Disabled
#1 : 1
Regulator Enabled
End of enumeration elements list.
SEL25 : Regulator Output Voltage Selection(Write Protect)\nSelect internal reference voltage level.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
1.5V
#01 : 1
1.8V
#10 : 2
2.5V
#11 : 3
2.5V
End of enumeration elements list.
EXTMODE : Regulator External Mode(Write Protect)\nUsers can output regulator output voltage in VREF pin if EXT_MODE is high.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
No connection with external VREF pin
#1 : 1
Connet to external VREF pin. Connect a 1uF to 10uF capacitor to AVSS will let internal voltage reference be more stable
End of enumeration elements list.
VREFTRIM : Internal Voltage Reference Trim(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 8 - 11 (4 bit)
access : read-write
LDO Control Register
address_offset : 0x70 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FASTWK : Fast Wake-up Control Bit (Write Protect)
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Fast Wake-up from Power-Down mode Disabled
#1 : 1
Fast Wake-up from Power-Down mode Enabled
End of enumeration elements list.
LDOLVL : LDO Output Voltage Select(Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
#00 : 0
1.2V
#01 : 1
1.6V
#10 : 2
1.8V
#11 : 3
1.8V
End of enumeration elements list.
LPRMEN : Low-power Run Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Low-Power runmode Enabled
#1 : 1
Low-Power runmode Disabled
End of enumeration elements list.
FMCLVEN : Flash Memory Low Voltage Mode Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Flash memory low voltage(1.2V) mode Enabled
#1 : 1
Flash memory low voltage(1.2V) mode Disabled
End of enumeration elements list.
Battery Voltage Divider Control Register
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BATDIV2EN : Battery Voltageg Divide 2 Enable Bit\nThis bit is used to enable/disable battery voltageg divider function.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Battery voltageg divide 2 function Disabled (default)
#1 : 1
Battery voltageg divide 2 function Enabled
End of enumeration elements list.
System Wake-up Status Register
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACMPWK : ACMP Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with ACMP wake-up event. This flag is cleared when Power-down mode is entered.
bits : 0 - 0 (1 bit)
access : read-only
I2C1WK : I2C1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 1 - 1 (1 bit)
access : read-only
I2C0WK : I2C0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with I2C0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 2 - 2 (1 bit)
access : read-only
TMR3WK : TMR3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR3 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 3 - 3 (1 bit)
access : read-only
TMR2WK : TMR2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR2 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 4 - 4 (1 bit)
access : read-only
TMR1WK : TMR1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 5 - 5 (1 bit)
access : read-only
TMR0WK : TMR0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested withTMR0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 6 - 6 (1 bit)
access : read-only
WDTWK : WDT Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with WDT wake-up event. This flag is cleared when Power-down mode is entered.
bits : 7 - 7 (1 bit)
access : read-only
BODWK : BOD Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with BOD wake-up event. This flag is cleared when Power-down mode is entered.
bits : 8 - 8 (1 bit)
access : read-only
SPI3WK : SPI3 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI3 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 9 - 9 (1 bit)
access : read-only
SPI2WK : SPI2 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI2 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 10 - 10 (1 bit)
access : read-only
SPI1WK : SPI1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 11 - 11 (1 bit)
access : read-only
SPI0WK : SPI0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with SPI0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 12 - 12 (1 bit)
access : read-only
UART1WK : UART1 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART1 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 13 - 13 (1 bit)
access : read-only
UART0WK : UART0 Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with UART0 wake-up event. This flag is cleared when Power-down mode is entered.
bits : 14 - 14 (1 bit)
access : read-only
RTCWK : RTC Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with a RTCalarm or tick time happened. This flag is cleared when Power-down mode is entered.
bits : 15 - 15 (1 bit)
access : read-only
GPIOWK : GPIO Wake-up Flag (Read Only)\nThis flag indicates that wake-up of device from Power-down mode was requested with GPIO wake-up event. This flag is cleared when Power-down mode is entered.
bits : 16 - 16 (1 bit)
access : read-only
Peripheral Reset Control Resister1
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPRST : Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.\nAbout the difference between CHIPRST and SYSRESETREQ(AIRCR[2]), please refer to section 6.2.2\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Chip normal operation
#1 : 1
Chip one-shot reset
End of enumeration elements list.
CPURST : Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Processor core normal operation
#1 : 1
Processor core one-shot reset
End of enumeration elements list.
PDMARST : PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
PDMA controller normal operation
#1 : 1
PDMA controllerreset
End of enumeration elements list.
HIRC0 Trim Control Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC0) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_IRC0TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 000 automatically.\nNote: HIRC0 auto trim cannot work normally inPower-down mode. These bits must be cleared before entering Power-down mode.
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#000 : 0
Disable HIRC0 auto trim function
#001 : 1
Enable HIRC0 auto trim function and trim HIRC to 11.0592 MHz
#010 : 2
Enable HIRC0 auto trim function and trim HIRC to 12 MHz
#011 : 3
Enable HIRC0 auto trim function and trim HIRC to 12.288 MHz
#100 : 4
Enable HIRC0 auto trim function and trim HIRC to 16 MHz
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 32.768 kHz clock
#01 : 1
Trim value calculation is based on average difference in 8 32.768 kHz clock
#10 : 2
Trim value calculation is based on average difference in 16 32.768 kHz clock
#11 : 3
Trim value calculation is based on average difference in 32 32.768 kHz clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC0 trim value before the frequency of HIRC0 locked.\nOnce the HIRC0 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC0 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC0TCTL[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC0 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC0TISTS[2]) would be set high and HIRC0 trim operation is continuously.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
HIRC0 Trim Interrupt Enable Register
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC0 trim value update limitation count reached and HIRC0 frequency still not locked on target frequency set by FREQSEL(SYS_IRC0TCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRC0TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_IRC0TSTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRC0TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_IRC0TSTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC0 Trim Interrupt Status Register
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC0 Frequency Lock Status\nThis bit indicates the HIRC0 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at frequency set by FREQSEL (SYS_IRC0TCTL[2:0])
#1 : 1
The internal high-speed oscillator frequency locked at frequency set by FREQSEL (SYS_IRC0TCTL[2:0])
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC0 trim value update limitation count reached and the HIRC0 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRC0TIEN[1]) is high, an interrupt will be triggered to notify that HIRC0 trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or internal high speed RC oscillator (HIRC0) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC0TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC0TCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRC0TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
HIRC1 Trim Control Register
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 36 MHz internal high speed RC oscillator (HIRC1) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_IRC1TCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote: HIRC1 auto trim cannot work normally inPower-down mode. These bits must be cleared before entering Power-down mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable HIRC1 auto trim function
#01 : 1
Reserved
#10 : 2
Enable HIRC1 auto trim function and trim HIRC to 36 MHz
#11 : 3
Reserved
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 32.768 kHz clock
#01 : 1
Trim value calculation is based on average difference in 8 32.768 kHz clock
#10 : 2
Trim value calculation is based on average difference in 16 32.768 kHz clock
#11 : 3
Trim value calculation is based on average difference in 32 32.768 kHz clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC1 trim value before the frequency of HIRC1 locked.\nOnce the HIRC1 locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of HIRC1 still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_IRC1TCTL[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit\nThis bit is used to control if stop the HIRC1 trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_IRC1TISTS[2]) would be set high and HIRC1 trim operation is continuously.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
HIRC1 Trim Interrupt Enable Register
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC1 trim value update limitation count reached and HIRC1 frequency still not locked on target frequency set by FREQSEL(SYS_IRC1TCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_IRC1TSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_IRC1TSTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_IRC1TSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_IRC1TSTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
HIRC1 Trim Interrupt Status Register
address_offset : 0x98 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : HIRC1 Frequency Lock Status\nThis bit indicates the HIRC1 frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal high-speed oscillator frequency doesn't lock at 36 MHz yet
#1 : 1
The internal high-speed oscillator frequency locked at 36 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that HIRC1 trim value update limitation count reached and the HIRC1 clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_IRC1TIEN[1]) is high, an interrupt will be triggered to notify that HIRC1 trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and HIRC1 frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 36 MHz internal high speed RC oscillator (HIRC1) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC1TCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC1TCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_IRC1TIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
MIRC Trim Control Register
address_offset : 0xA0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQSEL : Trim Frequency Selection\nThis field indicates the target frequency of 4 MHz internal medium speed RC oscillator (MIRC) auto trim.\nDuring auto trim operation, if clock error detected with CESTOPEN (SYS_MIRCTCTL[8]) is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.\nNote:MIRC auto trim cannot work normally inPower downn mode. These bits must be cleared before entering Power-down mode.
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#00 : 0
Disable MIRC auto trim function
#01 : 1
Reserved
#10 : 2
Enable MIRC auto trim function and trim HIRC to 4 MHz
#11 : 3
Reserved
End of enumeration elements list.
LOOPSEL : Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many 32.768 kHz clock.\nNote: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim value calculation is based on average difference in 4 32.768 kHz clock
#01 : 1
Trim value calculation is based on average difference in 8 32.768 kHz clock
#10 : 2
Trim value calculation is based on average difference in 16 32.768 kHz clock
#11 : 3
Trim value calculation is based on average difference in 32 32.768 kHz clock
End of enumeration elements list.
RETRYCNT : Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the MIRC trim value before the frequency of MIRC locked.\nOnce the MIRC locked, the internal trim value update counter will be reset.\nIf the trim value update counter reached this limitation value and frequency of MIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL (SYS_MIRCTCTL[1:0]) will be cleared to 00.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
#00 : 0
Trim retry count limitation is 64 loops
#01 : 1
Trim retry count limitation is 128 loops
#10 : 2
Trim retry count limitation is 256 loops
#11 : 3
Trim retry count limitation is 512 loops
End of enumeration elements list.
CESTOPEN : Clock Error Stop Enable Bit\nThis bit is used to control if stop the MIRC trim operation when 32.768 kHz clock error is detected.\nIf set this bit high and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation was stopped. If this bit is low and 32.768 kHz clock error detected, the status CLKERRIF (SYS_MIRCTISTS[2]) would be set high and MIRC trim operation is continuously.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
The trim operation is keep going if clock is inaccuracy
#1 : 1
The trim operation is stopped if clock is inaccuracy
End of enumeration elements list.
MIRC Trim Interrupt Enable Register
address_offset : 0xA4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TFAILIEN : Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while MIRC trim value update limitation count reached and MIRC frequency still not locked on target frequency set by FREQSEL(SYS_MIRCTCTL[1:0]).\nIf this bit is high and TFAILIF(SYS_MIRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable TFAILIF(SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU
#1 : 1
Enable TFAILIF(SYS_MIRCTSTS[1]) status to trigger an interrupt to CPU
End of enumeration elements list.
CLKEIEN : Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1, and CLKERRIF(SYS_MIRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Disable CLKERRIF(SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU
#1 : 1
Enable CLKERRIF(SYS_MIRCTSTS[2]) status to trigger an interrupt to CPU
End of enumeration elements list.
MIRC Trim Interrupt Status Register
address_offset : 0xA8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQLOCK : MIRC Frequency Lock Status\nThis bit indicates the MIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
The internal medium-speed oscillator frequency doesn't lock at 4 MHz yet
#1 : 1
The internal medium-speed oscillator frequency locked at 4 MHz
End of enumeration elements list.
TFAILIF : Trim Failure Interrupt Status\nThis bit indicates that MIRC trim value update limitation count reached and the MIRC clock frequency still doesn't be locked. Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically.\nIf this bit is set and TFAILIEN(SYS_MIRCTIEN[1]) is high, an interrupt will be triggered to notify that MIRC trim value update limitation count was reached. Write 1 to clear this to 0.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Trim value update limitation count does not reach
#1 : 1
Trim value update limitation count reached and MIRC frequency still not locked
End of enumeration elements list.
CLKERRIF : Clock Error Interrupt Status\nWhen the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 4 MHz internal medium speed RC oscillator (MIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy\nOnce this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_MIRCTCTL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_MIRCTCTL[8]) is set to 1.\nIf this bit is set and CLKEIEN(SYS_MIRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. Write 1 to clear this to 0.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Clock frequency is accuracy
#1 : 1
Clock frequency is inaccuracy
End of enumeration elements list.
Peripheral Reset Control Resister2
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPIORST : GPIO Controller Reset
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
GPIO module normal operation
#1 : 1
GPIO module reset
End of enumeration elements list.
TMR0RST : Timer0 Controller Reset
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer0 module normal operation
#1 : 1
Timer0 module reset
End of enumeration elements list.
TMR1RST : Timer1 Controller Reset
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer1 module normal operation
#1 : 1
Timer1 module reset
End of enumeration elements list.
TMR2RST : Timer2 Controller Reset
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer2 module normal operation
#1 : 1
Timer2 module reset
End of enumeration elements list.
TMR3RST : Timer3 Controller Reset
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer3 module normal operation
#1 : 1
Timer3 module reset
End of enumeration elements list.
DSRCRST : DSRC Controller Reset
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
#0 : 0
DSRCmodule normal operation
#1 : 1
DSRCmodule reset
End of enumeration elements list.
I2C0RST : I2C0 Controller Reset
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C0 module normal operation
#1 : 1
I2C0 module reset
End of enumeration elements list.
I2C1RST : I2C1 Controller Reset
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#0 : 0
I2C1 module normal operation
#1 : 1
I2C1 module reset
End of enumeration elements list.
SPI0RST : SPI0 Controller Reset
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI0 module normal operation
#1 : 1
SPI0 module reset
End of enumeration elements list.
SPI1RST : SPI1 Controller Reset
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI1 module normal operation
#1 : 1
SPI1 modulereset
End of enumeration elements list.
SPI2RST : SPI2 Controller Reset
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI2module normal operation
#1 : 1
SPI2modulereset
End of enumeration elements list.
SPI3RST : SPI3 Controller Reset
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
#0 : 0
SPI3module normal operation
#1 : 1
SPI3modulereset
End of enumeration elements list.
UART0RST : UART0 Controller Reset
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART0 module normal operation
#1 : 1
UART0 module reset
End of enumeration elements list.
UART1RST : UART1 Controller Reset
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
UART1 module normal operation
#1 : 1
UART1 module reset
End of enumeration elements list.
PWM0RST : PWM0 Controller Reset
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
PWM0 module normal operation
#1 : 1
PWM0 module reset
End of enumeration elements list.
ACMP01RST : Comparator Controller Reset
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Comparatormodule normal operation
#1 : 1
Comparatormodule reset
End of enumeration elements list.
ADCRST : ADC Controller Reset
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
ADC module normal operation
#1 : 1
ADC module reset
End of enumeration elements list.
SC0RST : SmartCard0 Controller Reset
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#0 : 0
SmartCardmodule normal operation
#1 : 1
SmartCardmodule reset
End of enumeration elements list.
SC1RST : SmartCard1 Controller Reset
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
SmartCardmodule normal operation
#1 : 1
SmartCardmodule reset
End of enumeration elements list.
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