FMC_ISPCTL (ISPCTL)

FMC_ISPTRG (ISPTRG)

FMC_DFBA (DFBA)

FMC_FTCTL (FTCTL)

FMC_ISPADDR (ISPADDR)

FMC_ISPSTS (ISPSTS)

FMC_KEY0 (KEY0)

FMC_KEY1 (KEY1)

FMC_KEY2 (KEY2)

FMC_KEYTRG (KEYTRG)

FMC_KEYSTS (KEYSTS)

FMC_KECNT (KECNT)

FMC_KPCNT (KPCNT)

FMC_ISPDAT (ISPDAT)

FMC_ISPCMD (ISPCMD)

ISPEN : ISP Enable Bit (Write Protect)\nISP function enable bit. Set this bit to enable ISP function.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BS : Boot Select (Write Protect) Set/clear this bit to select next booting from LDROM/APROM, respectively. This bit also functions as chip booting status flag, which can be used to check where chip booted from. This bit is initiated with the inversed value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPUEN : SPROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

APUEN : APROM Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CFGUEN : CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LDUEN : LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is set by hardware when a triggered ISP meets any of the following conditions: This bit needs to be cleared by writing 1 to it. (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region (11) KPROM is erased/programmed if KEYLOCK is set to 1 (12) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 Note: This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ISPGO : ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DFBA : Data Flash Base Address\nThis register indicates Data Flash start address. It is a read only register.\nThe Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
bits : 0 - 31 (32 bit)
access : read-only

FOM : Frequency Optimization Mode (Write Protect)\nThe Nano103 series supports adjustable flash access timing to optimize the flash access cycles in different working frequency.\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CACHEOFF : Flash Cache Disable Control (Write Protect)\nNote:This bit is write protected. Refer to the SYS_REGLCTL register.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ISPADDR : ISP Address\nThe Nano103 series is equipped with embedded flash. ISPADDR [1:0] must be kept 00 for ISP 32-bit operation. \nFor both CRC-32 Checksum Calculation and Flash All-One Verification commands, this field is the flash starting address for checksum calculation and 512 bytes address alignment is necessary.
bits : 0 - 31 (32 bit)
access : read-write

ISPBUSY : ISP Busy Flag (Read Only)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.\nThis bit is the mirror of ISPGO(FMC_ISPTRG[0]).
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CBS : Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0 [7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
bits : 1 - 2 (2 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PGFF : Flash Program with Fast Verification Flag(Read Only)\nThis bit is set if data is mismatched at ISP programming verification. This bit is clear by performing ISP flash erase or ISP read CID operation
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ISPFF : ISP Fail Flag (Write Protect) This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions: (1) APROM writes to itself if APUEN is set to 0. (2) LDROM writes to itself if LDUEN is set to 0. (3) CONFIG is erased/programmed if CFGUEN is set to 0. (4) SPROM is erased/programmed if SPUEN is set to 0 (5) SPROM is programmed at SPROM secured mode. (6) Page Erase command at LOCK mode with ICE connection (7) Erase or Program command at brown-out detected (8) Destination address is illegal, such as over an available range. (9) Invalid ISP commands (10) Vector address is mapping to SPROM region (11) KPROM is erased/programmed if KEYLOCK is set to 1 (12) APROM(not include Data Flash) is erased/programmed if KEYLOCK is set to 1 Note: This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 6 - 6 (1 bit)
access : read-write

ALLONE : Flash All-one Verification Flag This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete this bit also can be clear by writing 1
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

VECMAP : Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the flash memory or SRAM address {VECMAP[20:0], 9'h000} ~ {VECMAP[20:0], 9'h1FF}\nVECMAP [18:12] should be 0.
bits : 9 - 29 (21 bit)
access : read-only

SCODE : Security Code Active Flag This bit is set by hardware when detecting SPROM secured code is active at flash initiation, or software writes 1 to this bit to make secured code active this bit is clear by SPROM page erase operation.
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEY0 : KEY0 Data (Write Only)\nWrite KEY0 data to this register before KEY Comparison operation.
bits : 0 - 31 (32 bit)
access : write-only

KEY1 : KEY1 Data (Write Only)\nWrite KEY1 data to this register before KEY Comparison operation.
bits : 0 - 31 (32 bit)
access : write-only

KEY2 : KEY2 Data (Write Only)\nWrite KEY2 data to this register before KEY Comparison operation.
bits : 0 - 31 (32 bit)
access : write-only

KEYGO : KEY Comparison Start Trigger (Write Protection)\nWrite 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished. This trigger operation is valid while FORBID (FMC_KEYSTS [3]) is 0.\nNote:This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TCEN : Time-out Counting Enable Bit (Write Protection)\n10 minutes is at least for time-out, and average is about 20 minutes.\nNote:This bit is write-protected. Refer to the SYS_REGLCTL register.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYBUSY : KEY Comparison Busy (Read Only)
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KEYLOCK : KEY LOCK Flag\nThis bit is set to 1 if KEYMATCH (FMC_KEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection. This bit also can be set to 1 while \nCPU write 1 to KEYLOCK(FMC_KEYSTS[1]) or\nKEYFLAG(FMC_KEYSTS[4]) is 1 at power-on or reset or\nKEYENROM is programmed a non-0xFF value or\nTime-out event or\nFORBID(FMC_KEYSTS[3]) is 1\nSPROM write protect is depended on SPFLAG.\nCONFIG write protect is depended on CFGFLAG
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

KEYMATCH : KEY Match Flag(Read Only) This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM and cleared to 0 if KEYs are unmatched. This bit is also cleared to 0 while CPU writing 1 to KEYLOCK(FMC_KEYSTS[1]) or Time-out event or KPROM is erased or KEYENROM is programmed to a non-0xFF value. Chip is in Power-down mode.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FORBID : KEY Comparison Forbidden Flag(Read Only)\nThis bit is set to 1 whenKECNT(FMC_KECNT[4:0])is more than KEMAX (FMC_KECNT[12:8]) orKPCNT (FMC_KPCNT [2:0])is more than KPMAX (FMC_KPCNT [10:8]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KEYFLAG : KEY Protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [7:0] is not 0xFF at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM is programmed to a non-0xFF value.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CFGFLAG : CONFIG Write-protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [0] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SPFLAG : SPROM Write-protection Enable Flag(Read Only)\nThis bit is set while the KEYENROM [1] is 0 at power-on or reset. This bit is cleared to 0 by hardware while KPROM is erased. This bit is set to 1 by hardware while KEYENROM[1] is programmed to 0.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

KECNT : Error Key Entry Counter at Each Power-on (Read Only)\nKECNT is increased when entry keys is wrong in Security Key protection. KECNT is cleared to 0 if key comparison is matched or system power-on.
bits : 0 - 5 (6 bit)
access : read-only

KEMAX : Maximum Number for Error Key Entry at Each Power-on (Read Only)\nKEMAX is the maximum error key entry number at each power-on. When KEMAXROM of KPROM is erased or programmed, KEMAX will also be updated. KEMAX is used to limit KECNT(FMC_KECNT[5:0]) maximum counting. The FORBID (FMC_KEYSTS [3]) will be set to 1 when KECNT is more than KEMAX.
bits : 8 - 13 (6 bit)
access : read-only

KPCNT : Power-on Counter for Error Key Entry(Read Only)\nKPCNT is the power-on counting for error key entry in Security Key protection. KPCNT is cleared to 0 if key comparison is matched.
bits : 0 - 3 (4 bit)
access : read-only

KPMAX : Power-on Maximum Number for Error Key Entry (Read Only)\nKPMAX is the power-on maximum number for error key entry. When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated. KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting. The FORBID(FMC_KEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX
bits : 8 - 11 (4 bit)
access : read-only

ISPDAT : ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation.
bits : 0 - 31 (32 bit)
access : read-write

CMD : ISP CMD\nISP command table is shown below:\nThe other commands are invalid.
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

End of enumeration elements list.