\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0xC Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x14 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x1C Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x80 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
CRC Control Register
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRCEN : CRC Channel Enable Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CRC operation Enabled
End of enumeration elements list.
CRCRST : CRC Engine Reset Bit\nNote1: This bit will be cleared automatically.\nNote2: When operating in CPU mode, setting this bit will reload the seed value from CRC_SEED register as checksum initial value.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset the internal CRC state machine and internal buffer. The others contents of CRC_CTL register will not be cleared
End of enumeration elements list.
TRIGEN : Trigger Enable Bit\nThis bit is used to trigger the CRC DMA transfer.\nNote1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_DAT register.\nNote2: When CRC DMA transfer completed, this bit will be cleared automatically.\nNote3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped. User must reset all DMA channel before trigger DMA again.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CRC DMA data read or write transfer Enabled
End of enumeration elements list.
DATREV : Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function for writing data value in CRC_DTA register.\nNote: If the write data is 0xAABBCCDD, the bit order reverse for CRC data write in is 0x55DD33BB.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit order reverse for CRC data write in Disabled
#1 : 1
Bit order reverse for CRC data write in Enabled (per byte)
End of enumeration elements list.
CHKSREV : Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
Bit order reverse for CRC checksum Disabled
#1 : 1
Bit order reverse for CRC checksum Enabled
End of enumeration elements list.
DATFMT : Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DTA register.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#0 : 0
1's complement for CRC writes data in Disabled
#1 : 1
1's complement for CRC writes data in Enabled
End of enumeration elements list.
CHKSFMT : Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
#0 : 0
1's complementfor CRC checksum Disabled
#1 : 1
1's complement for CRC checksum Enabled
End of enumeration elements list.
DATLEN : CPU Write Data Length
This field indicates the CPU write data length only when operating in CPU mode.
Note1: This field is only valid when operating in CPU mode.
Note2: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA [7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA [15:0].
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
#00 : 0
The write data length is 8-bit mode
#01 : 1
The write data length is 16-bit mode
#10 : 2
The write data length is 32-bit mode
#11 : 3
Reserved
End of enumeration elements list.
CRCMODE : CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode.
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
#00 : 0
CRC-CCITT Polynomial Mode
#01 : 1
CRC-8 Polynomial Mode
#10 : 2
CRC-16 Polynomial Mode
#11 : 3
CRC-32 Polynomial Mode
End of enumeration elements list.
CRC DMA Current Source Address Register
address_offset : 0x14 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CSA : CRC DMA Current Source Address Bits (Read Only)\nThis field indicates the current source address where the CRC DMA transfer just occurs.
bits : 0 - 31 (32 bit)
access : read-only
CRC DMA Current Transfer Byte Count Register
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CBCNT : CRC DMA Current Remained Byte Count (Read Only)\nThis field indicates the current remained byte count of CRC DMA.\nNote: Setting the CRCRST (CRC_CTL[1]) bit to 1 will clear this register value.
bits : 0 - 15 (16 bit)
access : read-only
CRC DMA Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABTIEN : CRC DMA Read/Write Target Abort Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Target Abort interrupt signal while TABTIF (CRC_DMAINTSTS[0]) bit is set to 1.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Target abort interrupt Disabled during CRC DMA transfer
#1 : 1
Target abort interrupt Enabled during CRC DMA transfer
End of enumeration elements list.
TDIEN : CRC DMA Block Transfer Done Interrupt Enable Bit\nEnable this bit will generate the CRC DMA Transfer Done interrupt signal while TDIF (CRC_DMAINTSTS[1]) bit is set to 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Interrupt Disabled when CRC DMA transfer done
#1 : 1
Interrupt Enabled when CRC DMA transfer done
End of enumeration elements list.
CRC DMA Interrupt Status Register
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TABTIF : CRC DMA Read/Write Target Abort Interrupt Flag
This bit indicates that CRC bus has error or not during CRC DMA transfer.
Note1: This bit is cleared by writing 1 to it.
Note2: This bit indicates bus master received error response or not. If bus master received error response, it means that CRC transfer data from an invalid address or to an invalid adress .At this time target abort is happened.DMA will stop transfer and respond this event to user then CRC state machine goes to IDLE state. When target abort occurred, user must reset DMA before transfer those data again.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No bus error response received during CRC DMA transfer
#1 : 1
Bus error response received during CRC DMA transfer
End of enumeration elements list.
TDIF : CRC DMA Transfer Done Interrupt Flag
This bit indicates that CRC DMA transfer has finished or not.
Note1: This bit is cleared by writing 1 to it.
Note2: When CRC DMA transfer is done, TRIGEN (CRC_CTL[23]) will be cleared automatically.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Not finished if TRIGEN (CRC_CTL[23]) has enabled
#1 : 1
CRC transfer done if TRIGEN (CRC_CTL[23]) has enabled
End of enumeration elements list.
CRC DMA Source Address Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SA : CRC DMA Transfer Source Address Bits\nThis field indicates a 32-bit source address of CRC DMA.\nNote: The source address must be word alignment.
bits : 0 - 31 (32 bit)
access : read-write
CRC Write Data Register
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : CRC Write Data Bits
When operating in CPU mode, user can write data to this field to perform CRC operation.
When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written by user.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register are only DATA[7:0] bits if the write data length is 16-bit mode, the valid data in CRC_DAT register are only DATA[15:0] bits.
bits : 0 - 31 (32 bit)
access : read-write
CRC Seed Register
address_offset : 0x84 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEED : CRC Seed Value\nThis field indicates the CRC seed value.
bits : 0 - 31 (32 bit)
access : read-write
CRC Checksum Register
address_offset : 0x88 Bytes (0x0)
size : -1 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHECKSUM : CRC Checksum Results\nThis field indicates the CRC checksum result
bits : 0 - 31 (32 bit)
access : read-only
CRC DMA Transfer Byte Count Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BCNT : CRC DMA Transfer Byte Count \nThis field indicates a 16-bit total transfer byte count number of CRC DMA.
bits : 0 - 15 (16 bit)
access : read-write
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