\n
address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x20 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x100 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x120 Bytes (0x0)
size : 0x4 byte (0x0)
mem_usage : registers
protection : not protected
Timer 2 Control and Status Register
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTEN : Timer Counting Enable Bit\nNote3: Writing this bit 1 will not take any effect if RSTCNT (TIMERx_CTL[1]) is also set to 1 at the same time.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Stops/Suspends counting
#1 : 1
Starts counting
End of enumeration elements list.
RSTCNT : Timer Counter Reset Bit\nSetting this bit will reset the internal 8-bit prescale counter, 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[0]) to 0.\nNote: This bit will be auto cleared and takes at least 3 TIMERx_CLK clock cycles.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit
End of enumeration elements list.
WKEN : Wake-up Function Enable Bit\nIf this bit is set to 1, while CNTIF (TIMERx_INTSTS[0]) or CAPIF (TIMERx_INTSTS[1]) is 1, the timer interrupt signal will generate a wake-up trigger event to CPU.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#0 : 0
Wake-up function Disabled if timer interrupt signal generated
#1 : 1
Wake-up function Enabled if timer interrupt signal generated
End of enumeration elements list.
ICEDEBUG : ICE Debug Mode Acknowledge Disable Bit\nTimer counter will keep going no matter CPU is held by ICE or not.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#0 : 0
ICE debug mode acknowledgement affects TIMER counting
#1 : 1
ICE debug mode acknowledgement Disabled
End of enumeration elements list.
OPMODE : Timer Counting Mode Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#00 : 0
The Timer controller is operated in One-shot mode
#01 : 1
The Timer controller is operated in Periodic mode
#10 : 2
The Timer controller is operated in Toggle-output mode
#11 : 3
The Timer controller is operated in Continuous Counting mode
End of enumeration elements list.
ACTSTS : Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
#0 : 0
24-bit up counter is not active
#1 : 1
24-bit up counter is active
End of enumeration elements list.
TRGADC : Trigger ADC Enable Bit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger ADC.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger ADC.\nIf TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger ADC.
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger ADC Disabled
#1 : 1
Timer interrupt trigger ADC Enabled
End of enumeration elements list.
TRGPDMA : Timer Trigger PDMA EnableBit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PDMA.\nNote: If TRGSSEL (TIMERx_CTL[11]) is set to 0, the time-out interrupt signal will trigger PDMA.\nIf TRGSSEL (TIMERx_CTL[11]) is set to 1, the capture interrupt signal will trigger PDMA.
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PDMADisabled
#1 : 1
Timer interrupt trigger PDMAEnabled
End of enumeration elements list.
TRGSSEL : Trigger Source Selection\nIf this bit is set to 1, capture interrupt can trigger ADC, PDMA and PWM. Otherwise, time-out interrupt can trigger ADC, PDMA and PWM.
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#0 : 0
Time-out interrupt is used to trigger ADC, PDMA and PWM
#1 : 1
Capture interrupt is used to trigger ADC, PDMA and PWM
End of enumeration elements list.
EXTCNTEN : Event Counter Mode Enable Bit\nThis bit is for external counting pin function enabled. \nNote: When timer is used as an event counter, this bit should be set to 1 and HCLK as timer clock source.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#0 : 0
Event counter mode Disabled
#1 : 1
Event counter mode Enabled
End of enumeration elements list.
CNTPHASE : Timer External Count Phase
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#0 : 0
A Falling edge of external counting pin will be counted
#1 : 1
A Rising edge of external counting pin will be counted
End of enumeration elements list.
CNTDBEN : Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is set to 1, the edge detection of Tx pin is detected with de-bounce circuit.
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx (x= 0~3) pin de-bounce Disabled
#1 : 1
Tx (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
CAPEN : Timer External Capture Pin Enable Bit\nThis bit enables the Tx_EXT pin.
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin Disabled
#1 : 1
Tx_EXT (x= 0~3) pin Enabled
End of enumeration elements list.
CAPFUNCS : Capture Function Selection
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#0 : 0
External Capture Mode Enabled
#1 : 1
External Reset Mode Enabled
End of enumeration elements list.
CAPEDGE : Timer External Capture Pin Edge Detection\nFor timer counter reset function and free-counting mode of timer capture function, the configurations are:
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
#00 : 0
A Falling edge on Tx_EXT (x= 0~3) pin will be detected.\n1stfalling edge on TC pin triggers 24-bit timer to start counting, while 2nd falling edge triggers 24-bit timer to stop counting
#01 : 1
A Rising edge on Tx_EXT (x= 0~3) pin will be detected.\n1st rising edge on TC pin triggers 24-bit timer to start counting, while 2nd rising edge triggers 24-bit timer to stop counting
#10 : 2
Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.\nFalling edge on TC pin triggers 24-bit timer to start counting, while rising edge triggers 24-bit timer to stop counting
#11 : 3
Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.\nRising edge on TC pin triggers 24-bit timer to start counting, while falling edge triggers 24-bit timer to stop counting
End of enumeration elements list.
CAPCNTMD : Timer Capture Counting Mode Selection\nThis bit indicates the behavior of 24-bit up-counting timer while CAPEN (TIMERx_CTL[16]) is set to high.\nIf this bit is 0, the free-counting mode, the behavior of 24-bit up-counting timer is defined by OPMODE (TIMERx_CTL[5:4]) field. When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and the transition of TC pin matches the CAPEDGE (TIMERx_CTL[19:18]) setting, the value of 24-bit up-counting timer will be saved into register TIMERx_CAP.\nIf this bit is 1, Trigger-counting mode, 24-bit up-counting timer will be not counting and keep its value at 0. When CAPEN (TIMERx_CTL[16]) is set, CAPFUNCS (TIMERx_CTL[17]) is 0, and once the transition of external pin matches the 1st transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will start counting. And then if the transition of external pin matches the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, the 24-bit up-counting timer will stop counting. And its value will be saved into register TIMERx_CAP.
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#0 : 0
Capture with free-counting timer mode
#1 : 1
Capture with trigger-counting timer mode
End of enumeration elements list.
CAPDBEN : Timer External Capture Pin De-bounce Enable Bit\nNote1: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.\nNote2: For Timer 1 and 3, when INTRTGEN (TIMERx_CTL[24]) is high, the capture signal is from internal of chip and the de-bounce circuit would not take effect no matter this bit is high or low.
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin de-bounce Disabled
#1 : 1
Tx_EXT (x= 0~3) pin de-bounce Enabled
End of enumeration elements list.
CMPCTL : Timer Compared Mode Selection
If updated CMPDAT (TIMERx_CMP) value CNT (TIMERx_CNT), CNT (TIMERx_CNT) will be reset to default value. At the same time, prescale counter reloaded.
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
#0 : 0
The behavior selection in one-shot, periodic or Toggle-output mode Disabled
#1 : 1
The behavior selection in one-shot, periodic or Toggle-output mode Enabled
End of enumeration elements list.
INTRTGEN : Inter-timer Trigger Function EnableBit\nNote:In TIMERx+1_CTL, this bit is always 0.
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#0 : 0
Inter-timer trigger function Disabled
#1 : 1
Inter-timer trigger function Enabled
End of enumeration elements list.
INTRTGMD : Inter-timer Trigger Mode Selection\nNote:In TIMERx+1_CTL, this bit is always 0.
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
#0 : 0
TIMERx count the all input events from Tx pin
#1 : 1
TIMERx ignored the number of first incoming events based on EVNTDPCNT (TIMERx_ECTL[31:24])
End of enumeration elements list.
TRGPWM : Trigger PWM EnableBit\nIf this bit is set to 1, timer time-out interrupt or capture interrupt can trigger PWM.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer interrupt trigger PWM Disabled
#1 : 1
Timer interrupt trigger PWM Enabled
End of enumeration elements list.
DSRCCTLF : DSRC Control Timer Flag (Read Only)\nThis flag high indicates this timer is being controlled by DSRC. When DSRCCTLF is 1, write operation to register of this timer wouldn't take any effect.\nNote1:This bit is read only. Write operation wouldn't take any effect.\nNote2: This bit is only valid in Timer2. In Timer0, Timer1 and Timer3, read this bit always get 0.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
#0 : 0
DSRC control Timer Disabled
#1 : 1
DSRC control Timer Enabled
End of enumeration elements list.
Timer 2 Interrupt Status Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTIF : Timer Interrupt Status\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
No effect
#1 : 1
CNT (TIMERx_CNT[23:0])value matches the CMPDAT (TIMERx_CMP[23:0]) value
End of enumeration elements list.
CAPIF : Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\nNote3: If a new incoming capture event detected before CPU clearing the CAPIF status, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin interrupt did not occur
#1 : 1
Tx_EXT (x= 0~3) pin interrupt occurred
End of enumeration elements list.
TWKF : Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer does not cause CPU wake-up
#1 : 1
CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated
End of enumeration elements list.
CAPDATOF : Capture Data Overflow Flag\nThis status is to indicate there is a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status.\nIf the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.\nNote: This bit is cleared by writing 1 to it.
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
#0 : 0
New incoming capture event didn't detect before CPU clearing CAPIF (TIMERx_INTSTS[1]) status
#1 : 1
New incoming capture event detected before CPU clearing CAPIF (TIMERx_INTSTS[1]) status
End of enumeration elements list.
CAPFEDF : Capture Falling Edge Detected Flag\nThis flag indicates theedge detected on Tx_EXT pin is rising edge or falling edge.\nNote1: The timer updates this flag when it updates the Timer Capture Data (TMR_CAP[23:0]) value.\nNote2:When a new incoming capture event detected before CPU clearing the CAPIF (TIMERx_INTSTS[1]) status, Timer will keep this bit unchanged.
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#0 : 0
Rising edge detected on Tx_EXT pin
#1 : 1
Falling edge detected on Tx_EXT pin
End of enumeration elements list.
Timer 3 Control and Status Register
address_offset : 0x100 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Pre-Scale Counter Register
address_offset : 0x104 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Compare Register
address_offset : 0x108 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Interrupt Enable Register
address_offset : 0x10C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Interrupt Status Register
address_offset : 0x110 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Counter Data Register
address_offset : 0x114 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Capture Data Register
address_offset : 0x118 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 3 Extended Control Register
address_offset : 0x120 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Timer 2Counter Data Register
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNT : Timer Counter Data (Read)\nCounter Reset (Write)\nUser can write any value to TIEMRx_CNT to reset internal 24-bit timer up-counter and 8-bit pre-scale counter. This reset operation wouldn't affect any other timer control registers and circuit. After reset completed, the 24-bit timer up-counter and 8-bit pre-scale counter restart the counting based on the TIMERx_CTL register setting.
bits : 0 - 23 (24 bit)
access : read-write
RSTACT : Reset Active\nThis bit indicates if the counter reset operation active.\nWhen user write this register, timer starts to reset its internal 24-bit timer up-counter and 8-bit pre-scale counter to 0. At the same time, timer set this flag to 1 to indicate the counter reset operation is in progress. Once the counter reset operation done, timer clear this bit to 0 automatically.\nNote: This bit is read only. Write operation wouldn't take any effect.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
#0 : 0
Reset operation is done
#1 : 1
Reset operation triggered by writing TIMERx_CNT is in progress
End of enumeration elements list.
Timer 2 Capture Data Register
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CAPDAT : Timer Capture Data Register\nWhen CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 0, and the transition on Tx_EXT pin matched the CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.\nWhen CAPEN (TIMERx_CTL[16]) bit is set, CAPFUNCS (TIMERx_CTL[17]) bit is 0, CAPCNTMD (TIMERx_CTL[20]) bit is 1, and the transition on Tx_EXT pin matched the 2nd transition of CAPEDGE (TIMERx_CTL[19:18]) setting, CAPIF (TIMERx_INTSTS[1]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.
bits : 0 - 23 (24 bit)
access : read-only
Timer 2Extended Control Register
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVNTDPCNT : Event Drop Count\nThis field indicates timer how many events dropped after inter-timer trigger function enable.\nFor example, if user configured EVNTDPCNT to 7, timer would drop 7 first incoming events and starts the inter-timer trigger operation when it get 8th event.\nNote: ECNTDPCNT only takes effect when INTRTGEN (TIMERx_CTL[24]) INTRTGMD (TIMERx_CTL[25]) are both set to 1.
bits : 24 - 31 (8 bit)
access : read-write
Timer 2 Pre-Scale Counter Register
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSC : Prescale Counter\nNote: If the PSC value is changed, CNT (TIMERx_CNT) is reset to 0 and prescale counter is reloaded.
bits : 0 - 7 (8 bit)
access : read-write
Timer 2 Compare Register
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPDAT : Timer Compared Value\nCMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value, the CNTIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.\nNote1: Never write 0x0 or 0x1 in CMPDAT, or the core will run into unknown state.\nNote2:When the timer is operating in Continuous Counting mode (OPMODE (TIMERx_CTL[5:4] is 11), the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field. \nNote3: Whenthe timer is not operating inContinuous Counting mode (OPMODE (TIMERx_CTL[5:4] is not 11), the 24-bit up counter will restart counting from 0 and usethe newest CMPDAT value as the timer compared value when user writes a new value into the CMPDAT field.In addition, the prescale counter will be reloaded.
bits : 0 - 23 (24 bit)
access : read-write
Timer 2 Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTIEN : Timer Interrupt EnableBit\nNote:If this bit is enabled, when the timer interrupt flag CNTIF(TIMERx_INTSTS[0]) is set to 1, the timer interrupt signal is generated and informed to CPU.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : 0
Timer Interrupt Disabled
#1 : 1
Timer Interrupt Enabled
End of enumeration elements list.
CAPIEN : Timer External Capture Interrupt Enable Bit\nNote:CAPIEN is used to enable timer external interrupt. If CAPIEN is enabled, the timer will rise an interrupt when CAPIF (TIMERx_INTSTS[1]) is 1.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#0 : 0
Tx_EXT (x= 0~3) pin detection Interrupt Disabled
#1 : 1
Tx_EXT (x= 0~3) pin detection Interrupt Enabled
End of enumeration elements list.
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