UART_DAT

UART_INTSTS

UART_TRSR

UART_FIFOSTS

UART_MODE

UART_TOUT

UART_BAUD

UART_IRDA

UART_ATLCTL

UART_FUNCSEL

UART_BRCOMPAT

UART_CTRL

UART_WKUPEN

UART_WKUPSTS

UART_LINE

UART_INTEN

DAT : Receive /Transmit Buffer\nWrite Operation:\nBy writing one byte to this register, the data byte will be stored in transmitter FIFO. The UART Controller will send out the data stored in transmitter FIFO top location through the UART_DAT.\nRead Operation:\nBy reading this register, the UART will return an 8-bit data received from receiving FIFO.
bits : 0 - 7 (8 bit)
access : read-only

RDAIF : Receive Data Available Interrupt Flag (Read Only)\nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.\nNote: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_LINE[9:8])
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THREIF : Transmit Holding Register Empty Interrupt Flag (Read Only)\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.\nNote: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty)
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RLSIF : Receive Line Interrupt Flag (Read Only)\nThis bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set). If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.\nNote2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.\nNote3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_TRSR[0]) are cleared.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

MODEMIF : MODEM Interrupt Flag (Read Only) Channel \nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEM[18]).
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXTOIF : Rime-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC. If RXTOIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.\nNote: This bit is read only and user can read UART_DAT (RX is in active) to clear it
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BUFERRIF : Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[8]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5])is set, the transfer is not correct. If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.\nNote:This bit is read only. This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[8]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[8]).
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WKUPIF : Wake-up Interrupt Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by one of UART controller wake-up event.\nNote1: If WKDATEN (UART_INTEN[6]) is enabled, the wake-up interrupt is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to one of UART_WKUPSTS[4:0] (THRTOWKSTS or THRWKSTS or CTSWKSTS or DATWKSTS or ADRWKSTS).
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRIF : Auto-baud Rate Interrupt Status Flag (Read Only) This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[7]) is set then the auto-baud rate interrupt will be generated. Note1: This bit is read only, but can be cleared by writing 1 to ABRDTOIF (UART_TRSR[2]) or ABRDIF (UART_TRSR[1]). Note2: This bit is cleared when both the ABRDTOIF and ABRDIF are cleared.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LINIF : LIN Interrupt Status Flag (Read Only) This bit is set when the LIN TX header transmitted, RX header received or the SIN does not equal SOUT and if LINIEN(UART_INTEN[8]) is set then the LIN interrupt will be generated. Note1: This bit is read only, but can be cleared by it by writing 1 to BITEF (UART_TRSR[5]), LINTXIF (UART_TRSR[3]) or LINRXIF (UART_TRSR[4]). Note2: This bit is cleared when both the BITEF, LINTXIF and LINRXIF are cleared.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADDRDETF : RS-485 Address Byte Detection Status Flag (Read Only)\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRDIF : Auto-baud Rate Interrupt (Read Only) This bit is set to logic 1 when auto-baud rate detect function finished. Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ABRDTOIF : Auto-baud Rate Time-out Interrupt(Read Only) Note1:This bit is set to logic 1 in Auto-baud Rate Detect mode and the baud rate counter is overflow. Note2: This bit is read only, but can be cleared by writing 1 to it.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LINTXIF : LIN TX Interrupt Flag (Read Only) This bit is set to logic 1 when LIN transmitted header field. The header may be break field or break field + sync field or break field + sync field + PID field , it can be choose by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

LINRXIF : LIN RX Interrupt Flag (Read Only) This bit is set to logic 1 when received LIN header field. The header may be break field or break field + sync field or break field + sync field + PID field , and it can be choose by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BITEF : Bit Error Detect Status Flag (Read Only)\nAt TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state is not equal to the output pin (SOUT) state, BITEF will be set.\nWhen occur bit error, hardware will generate an interrupt to CPU (LININT).
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXBUSY : Receive Busy Status(Read Only)\nNote: The user can use this to check the busy status in receiver mode. If the user wants to enter power down, this bit shall be confirm in Idle state and there is 2 UART clock latency for receiver pin.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

SLVSYNCF : LIN RX SYNC Error Flag (Read Only) This bit is set to logic 1 when LIN received incorrect SYNC field. User can choose the header by setting LINHSEL (UART_ATLCTL[5:4]) register. Note: This bit is read only, but can be cleared by writing 1 to LINRXIF.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXOVIF : RX Overflow Error Status Flag (Read Only) This bit is set when RX FIFO overflow. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, this bit will be set. Note:This bit is read only, but can be cleared by writing 1 to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXEMPTY : Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high. It will be cleared when UART receives any new data.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXFULL : Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

PEF : Parity Error State Status Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid parity bit . Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

FEF : Framing Error Flag (Read Only) This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, the stop bit following the last data bit or parity bit is detected as logic 0). Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 5 - 5 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

BIF : Break Interrupt Flag( Read Only) This bit is set to logic 1 whenever the received data input (RX) is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of start bit + data bits + parity + stop bits). Note: This bit is read only, but can be cleared by writing '1' to it.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXOVIF : TX Overflow Error Interrupt Status Flag (Read Only) If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1. Note:This bit is read only, but can be cleared by writing 1 to it.
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXEMPTY : Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high. It will be cleared when writing data into DAT (TX FIFO not empty).
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXFULL : Transmitter FIFO Full (Read Only) This bit indicates TX FIFO full or not. Note:This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
bits : 10 - 10 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TXENDF : Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote:This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
bits : 11 - 11 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

RXPTR : RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device, RXPTR increases one. When one byte of RX FIFO is read by CPU, RXPTR decreases one.\nThe Maximum value shown in RXPTR is 15. When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0. As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
bits : 16 - 20 (5 bit)
access : read-only

TXPTR : TX-fIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT, TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.\nThe Maximum value shown in TXPTR is 15. When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0. As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
bits : 24 - 28 (5 bit)
access : read-only

RTSACTLV : nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSSTS : nRTS Pin State (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSACTLV : nCTS Trigger Level\nThis bit defines the active level state of nCTS pin input.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSSTS : nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

CTSDETF : Detect nCTS State Change Flag (Read Only) This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]). Note: This bit is read only, but it can be cleared by writing 1 to it.
bits : 18 - 18 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

TOIC : Time-out Comparator Note1: Fill all 0 to this field indicates to disable this function. Note2: The real time-out value is TOIC + 1. Note3: The counting clock is baud rate clock. Note4: The UART data format is start bit + 8 data bits + parity bit + stop bit, although software can configure this field by any value but it is recommend to fill this field great than 0xA.
bits : 0 - 8 (9 bit)
access : read-write

DLY : TX Delay Time Value This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time. Note1: Fill all 0 to this field indicates to disable this function. Note2: The real delay value is DLY. Note3:The counting clock is baud rate clock.
bits : 16 - 23 (8 bit)
access : read-write

BRD : Baud Rate Divider \nThe field indicates the baud rate divider. This filed is used in baud rate calculation. The detail description is shown inUART Controller Baud Rate Generation.
bits : 0 - 15 (16 bit)
access : read-write

DIV16EN : Divider 16 Enable Control Note: In IrDA mode, this bit must clear to 0 .
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXEN : IrDA Receiver/Transmitter Selection Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXINV : IrDA Inverse Transmitting Output Signal
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXINV : IrDA Inverse Receive Input Signal
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRKFL : LIN TX Break Field Count \nThe field contains 3-bit LIN TX break field count.\nNote: The break field length is BRKFL + 8.
bits : 0 - 2 (3 bit)
access : read-write

LINHSEL : LIN Header Selection
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINRXEN : LIN RX Enable Control\nWhen LIN RX mode enabled and received a break field or sync field or PID field (Select by LIN_Header_SEL), the controller will generator a interrupt to CPU (LININT)
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINTXEN : LIN TX Header Trigger EnableBit The LIN TX header can be break field or break and sync field or break, sync and frame ID field , it is depend on setting LINHSEL (UART_ATLCTL[5:4]). Note1: This bit will be cleared automatically and generate a interrupt to CPU (LININT). Note2:When transmitter header field (it may be break or break + sync or break + sync + frame ID selected by LINHSEL (UART_ATLCTL[5:4]) field) transfer operation finished, this bit will be cleared automatically. Note3: If user wants to receive transmit data, it recommended to enable LINRXEN bit.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BITERREN : Bit Error Detect EnableBit
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485NMM : RS-485 Normal Multi-drop Operation Mode (NMM)\nNote: It cannot be active with RS-485_AAD operation mode.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AAD : RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS485NMM operation mode.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RS485AUD : RS-485 Auto Direction Function (AUD)\nNote: It can be active with RS485AAD or RS485NMM operation mode.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADDRDEN : RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode. \nNote: This bit is used for RS-485 any operation mode.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ADRMPID : Address / PID Match Value Register\nWhen in the RS-485 Function Mode, this field contains the RS-485 address match values.\nWhen in the LIN Function mode, this field contains the LIN protected identifier field, software fills ID0~ID5 (PID [5:0]), hardware will calculate P0 and P1.\n\nNote: This field is used for RS-485 auto address detection mode or used for LIN protected identifier field (PID).
bits : 24 - 31 (8 bit)
access : read-write

FUNCSEL : Function Selection
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BRCOMPAT : Baud Rate Compensation Patten\nThese 9bits are used to define the relative bit is compensated or not. BRCOMPAT[7:0] is used to define the compensation of D[7:0] and BRCOMPAT{[8] is used to define the parity bit.
bits : 0 - 8 (9 bit)
access : read-write

BRCOMPDEC : Baud Rate Compensation Decrease
bits : 31 - 31 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXRST : RX Field Software Reset\nWhen RXRST (UART_CTRL[0]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXRST : TX Field Software Reset\nWhen TXRST (UART_CTRL[1]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote: This bit will automatically clear at least 3 UART peripheral clock cycles
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXOFF : Receiver Disable Bit Note1:In RS-485 NMM mode, user can set this bit to receive data before detecting address byte. Note2: In RS-485 AAD mode, this bit will be setting to 1 automatically. Note3: In RS-485 AUD mode and LIN break + sync +PID header mode, hardware will control data automatically, so don't fill any value to this bit.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXOFF : Transfer Disable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATORTSEN : nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_LINE[13:12]), the UART will de-assert nRTS signal.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ATOCTSEN : nCTS Auto-flow Control Enable Bit\nNote:When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXDMAEN : RX DMA Enable Bit\nThis bit can enable or disable RX DMA service.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXDMAEN : TX DMA Enable Bit\nThis bit can enable or disable TX DMA service.
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FTOEN : Frame Time Out Enable Bit\nThis bit is used to enable the timer counter even the FIFO is still empty.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRDEN : Auto-baud Rate Detect EnableBit\nNote: When the auto-baud rate detect operation finishes, hardware will clear this bit and the associated interrupt (ABRIF) will be generated (If ABRIEN (UART_INTEN [7]) be enabled).
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRDBITS : Auto-baud Rate Detect Bit Length\nNote: The calculation of bit number includes the START bit.
bits : 13 - 14 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKCTSEN : CTSn Wake-up Enable Bit\nWhen the system is in power-down mode, an external nCTS change will wake-up system from power-down mode.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKDATEN : Incoming Data Wake-up Enable Bit Note: Hardware will clear this bit when the incoming data wake-up operation finishes and system clock work stable.
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKTHREN : FIFO Threshold Reach Wake-up Enable Bit\nNote: It is suggest the function is enabled in UART mode and the UART clock is selected in 32K.
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKTHRTOEN : FIFO Threshold Reach Time Out Wake-up Enable Bit\nNote: It is suggest the function is enabled when the WKTHREN (UART_WKUPEN[2]) is set to 1.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKADRMEN : RS-485 Address Match Wake-up Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CTSWKSTS : nCTS Wake-up Flag (Read Only)\nNote1: If WKCTSEN (UART_ WKUPEN [0])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATWKSTS : Data Wake-up Flag (Read Only)\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_ WKUPEN [1]) is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRWKSTS : Threshold Wake-up Flag (Read Only)\nNote1: If WKTHREN (UART_ WKUPEN [2])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

THRTOWKSTS : Threshold Wake-up Time Out Flag (Read Only)\nNote1: If WKTHRTOEN (UART_ WKUPEN [3])is enabled, the wake-up function is generated.\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

ADRWKSTS : RS-485 Address Byte Detection Wake-up Flag (Read Only)\nNote1: If WKADRMEN (UART_WKUPEN[4])is enabled, the wake-up function is generated.\nNote2: This field is used for RS-485 function mode and ADDRDEN (UART_ATLCTL[19]) is set to 1 to enable Address detection mode .\nNote2: This bit is read only, but can be cleared by writing '1' to it.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

WLS : Word Length Selection\nThis field sets UART word length.
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NSB : Number of STOP Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PBE : Parity Bit EnableBit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data.
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EPE : Even Parity EnableBit\nNote:This bit has effect only when PBE (UART_LINE[3]) is set.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SPE : Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BCB : Break Control Bit\nNote: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RFITL : RX FIFO Interrupt Trigger Level When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated). Note: When operating in IrDA mode or RS-485 mode, the RFITL must be set to 0 .
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RTSTRGLV : nRTS Trigger Level for Auto-flow Control Use\nNote: This field is used for auto nRTS flow control.
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RDAIEN : Receive Data Available Interrupt Enable Bit
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

THREIEN : Transmit Holding Register Empty Interrupt Enable Bit
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RLSIEN : Receive Line Status Interrupt Enable Bit
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

MODEMIEN : Modem Status Interrupt Enable Bit
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

RXTOIEN : RX Time-out Interrupt Enable Bit
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BUFERRIEN : Buffer Error Interrupt Enable Bit
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

WKUPIEN : Wake-up Interrupt EnableBit Note: Hardware will clear one of the wake-up status bits in UART_WKUPSTS when the wake-up operation finishes and system clock work stable.
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

ABRIEN : Auto-baud Rate Interrupt Enable Bit
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LINIEN : LIN Bus Interrupt Enable Bit\nNote:This bit is used for LIN function mode.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

TXENDIEN : Transmitter Empty FInterrupt Enable Bit\nNote: If the bit is enabled, there is interrupt event when the TXENDF (UART_FIFOSTS[11]) is actived.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.